From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BDD17404E; Sun, 7 Jun 2026 08:48:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780822112; cv=none; b=W+A1UWg4TYuFmZKf0/CyJmgQWlwbqgCeHZXp3BWfqPS2KBeLb0jxAxOMI6VL6wrfZusacCCTk6l159DYLaw0UI2h4aO3fqe6Yq+qmzlIkjbZgjaqjrROqTgAuQtW5t2AB39rJCRqhuGs2LJVvIPgfE35HCKRwnX/8SIFPE1zUrI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780822112; c=relaxed/simple; bh=kZgPsZB4Y7dtuhyYaS+8LCL1SC9e7xH6JgOGoG8isGA=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=lmeGrnhF3/T0JTIFf+mhw7j/sRRGsphj/0qpI161d5LWEhPyzFI2MATmntsP8eqJyGF2Jcvwo6/mBYUeABn2mTPwrOL3PsrPIJXeoUEhTX0/lk437s8lSgA+BqzGRztEo5HNWQZq97WVaBwWy1wJD6MPYvcsoGtrn6ox4ijfn28= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=U4UdCNYy; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="U4UdCNYy" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C9CC11F00893; Sun, 7 Jun 2026 08:48:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780822111; bh=kZgPsZB4Y7dtuhyYaS+8LCL1SC9e7xH6JgOGoG8isGA=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=U4UdCNYyss7mbf96SJnjIE9hiG17oZb/DVjMdxkUROaHqSoziNNReXH5Ul4zQWcO8 9BfUadQ6M3sGXO+YuOZ4s3nenx74cFEzMLvetFg+xUBeb3US+imB0hZtuxW2YEZXsx H+h49By0jqi+Of/8u1qtxQLHQL4oQLn4MrWxtZ3E+pydxNTWAr3B7AwbxDNEI1tdsb sS2HlayNB6v16d0zL4GWDY5k3RAS4slYXNWLlMUlVTdleACJ8YusiFlE+BqOxz2pmT 2sbKK2XLmI6EC1r3WZFOKXRT9gMwaKu/x1alFGhlFp2uK6zn5IeY7YAQdyz4U4k6lB OtnzQy2vUR21A== Date: Sun, 7 Jun 2026 10:48:26 +0200 From: Krzysztof Kozlowski To: Krishna Chaitanya Chundru Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Bjorn Andersson , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH v2 2/3] dt-bindings: PCI: qcom,pcie-sm8550: Add Eliza compatible Message-ID: <20260607-devious-active-bobcat-1078ab@quoll> References: <20260601-eliza-v2-0-6b44c9c23d5e@oss.qualcomm.com> <20260601-eliza-v2-2-6b44c9c23d5e@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20260601-eliza-v2-2-6b44c9c23d5e@oss.qualcomm.com> On Mon, Jun 01, 2026 at 10:59:45PM +0530, Krishna Chaitanya Chundru wrote: > PCIe controller present in Eliza SoC is backwards compatible with the > controller present in Eliza SoC. Hence, add the compatible with SM8550 Eliza SoC is compatible with itself? > fallback. Why reg, clocks and interrupts are flexible? Are there different variants within Eliza SoC, e.g. one without msi? Best regards, Krzysztof