From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-183.mta1.migadu.com (out-183.mta1.migadu.com [95.215.58.183]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 19CA83CF69E for ; Tue, 9 Jun 2026 06:02:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.183 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780984959; cv=none; b=D+nia31NhxhevNr9ZL+hkTpg9aKFLLg768WLc4LSSaYHVKzd16Biruie0CtV7TFicO6UFBK/76E+mvTKHapvASj7ty2nSMdNbVWqimRWck8MbcpKC2hG/BaYjrdLix61x5fDX/HF4PN8oBtxiUohJsxgXcWeCo7N43hyZUQLBqM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780984959; c=relaxed/simple; bh=VrttyV9D+qBeS0hxU4VlV2uLCj1nw4zBG5ULHu2FIE8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kbvBD9qwZyXnF/d8BCa+yA1rqw1vXvBeKBIyTCmqdYrXfWKiP9sJSQ1l0/A7P7k2XzRzJTKMyoN7JEYjyn9wg2Hdbf83ohkUzvj9bmF2S2/sXTsoqY8IlKgeAUze9tQC1QliJPyklxnE1ryUEh6YN/wynuNUb+xED/hiG49A9vY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=ekI97+OL; arc=none smtp.client-ip=95.215.58.183 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="ekI97+OL" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1780984956; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dI3T9Syv/F7UBtrHfN9ztjqJivTsyiuB0g714VMRlRI=; b=ekI97+OLYDLY5IUXpxCC+SN10+OdASUqSS0n/O5Soyx/8FvkpFG636XaQZL3m5MHgGDUxu 9pN34vht5d1DFjwSBfkCc84u+E+86Kt8WuP2dM6TAw/DNBedYxbGuo4/XAoSEm5TtnXh68 GGYqs3N/43exj/PEq/cqV4k8V9bt+zk= From: Atish Patra Date: Mon, 08 Jun 2026 23:01:26 -0700 Subject: [PATCH v6 12/21] RISC-V: perf: Add a mechanism to defined legacy event encoding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260608-counter_delegation-v6-12-285b72ed65a9@meta.com> References: <20260608-counter_delegation-v6-0-285b72ed65a9@meta.com> In-Reply-To: <20260608-counter_delegation-v6-0-285b72ed65a9@meta.com> To: James Clark , Rob Herring , Atish Patra , Arnaldo Carvalho de Melo , Jiri Olsa , Will Deacon , Mark Rutland , Anup Patel , Namhyung Kim , Paul Walmsley , Krzysztof Kozlowski , Ian Rogers Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Migadu-Flow: FLOW_OUT From: Atish Patra RISC-V ISA doesn't define any standard event encodings or specify any event to counter mapping. Thus, event encoding information and corresponding counter mapping fot those events needs to be provided in the driver for each vendor. Add a framework to support that. The individual platform events will be added later. Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 54 +++++++++++++++++++++++++++++++++++++++++- include/linux/perf/riscv_pmu.h | 13 ++++++++++ 2 files changed, 66 insertions(+), 1 deletion(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 57ab15beab3e..46a25979e95e 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -379,6 +379,56 @@ static int pmu_sbi_check_event_info(void) return result; } +/* + * Vendor specific PMU events. + */ +struct riscv_pmu_event { + u64 event_id; + u32 counter_mask; +}; + +struct riscv_vendor_pmu_events { + unsigned long vendorid; + unsigned long archid; + unsigned long implid; + const struct riscv_pmu_event *hw_event_map; + const struct riscv_pmu_event (*cache_event_map)[PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX]; +}; + +#define RISCV_VENDOR_PMU_EVENTS(_vendorid, _archid, _implid, _hw_event_map, _cache_event_map) \ + { .vendorid = _vendorid, .archid = _archid, .implid = _implid, \ + .hw_event_map = _hw_event_map, .cache_event_map = _cache_event_map }, + +static struct riscv_vendor_pmu_events pmu_vendor_events_table[] = { +}; + +static const struct riscv_pmu_event *current_pmu_hw_event_map; +static const struct riscv_pmu_event (*current_pmu_cache_event_map)[PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX]; + +static void rvpmu_vendor_register_events(void) +{ + int cpu = raw_smp_processor_id(); + unsigned long vendor_id = riscv_cached_mvendorid(cpu); + unsigned long impl_id = riscv_cached_mimpid(cpu); + unsigned long arch_id = riscv_cached_marchid(cpu); + + for (int i = 0; i < ARRAY_SIZE(pmu_vendor_events_table); i++) { + if (pmu_vendor_events_table[i].vendorid == vendor_id && + pmu_vendor_events_table[i].implid == impl_id && + pmu_vendor_events_table[i].archid == arch_id) { + current_pmu_hw_event_map = pmu_vendor_events_table[i].hw_event_map; + current_pmu_cache_event_map = pmu_vendor_events_table[i].cache_event_map; + break; + } + } + + if (!current_pmu_hw_event_map || !current_pmu_cache_event_map) { + pr_info("No default PMU events found\n"); + } +} + static void rvpmu_sbi_check_event(struct sbi_pmu_event_data *edata) { struct sbiret ret; @@ -1643,8 +1693,10 @@ static int __init rvpmu_devinit(void) */ if (riscv_isa_extension_available(NULL, SSCCFG) && riscv_isa_extension_available(NULL, SMCDELEG) && - riscv_isa_extension_available(NULL, SSCSRIND)) + riscv_isa_extension_available(NULL, SSCSRIND)) { static_branch_enable(&riscv_pmu_cdeleg_available); + rvpmu_vendor_register_events(); + } if (!(riscv_pmu_sbi_available_boot() || riscv_pmu_cdeleg_available_boot())) return 0; diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index f82a28040594..6c75106989b6 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -28,6 +28,19 @@ #define RISCV_PMU_CONFIG1_GUEST_EVENTS 0x1 +#define HW_OP_UNSUPPORTED 0xFFFF +#define CACHE_OP_UNSUPPORTED 0xFFFF + +#define PERF_MAP_ALL_UNSUPPORTED \ + [0 ... PERF_COUNT_HW_MAX - 1] = {HW_OP_UNSUPPORTED, 0x0} + +#define PERF_CACHE_MAP_ALL_UNSUPPORTED \ +[0 ... C(MAX) - 1] = { \ + [0 ... C(OP_MAX) - 1] = { \ + [0 ... C(RESULT_MAX) - 1] = {CACHE_OP_UNSUPPORTED, 0x0} \ + }, \ +} + struct cpu_hw_events { /* currently enabled events */ int n_events; -- 2.53.0-Meta