From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-177.mta1.migadu.com (out-177.mta1.migadu.com [95.215.58.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 293173CF1F8 for ; Tue, 9 Jun 2026 06:02:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.177 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780984979; cv=none; b=KTSmnMkqv2TWyPR4ZzB0bpZe/niAVE+Zn7X3HtdI3xQcg7/Gzez9o+/O4iAP7S7dMeAI8DCIjHfMlnn6xCUt784tSiW57q4FCVBUUoBkwSbqaUhvZvtOMLclaVAyGLs8+2A/w24efSbrpfs5bGBFcC+VJg0broWEbkwcnshamM8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780984979; c=relaxed/simple; bh=BHR1e41gLgqpbFojagMPR+XYPEIf8v0+NW6a44ZbZ30=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hKYV0eyyHnjfgoGo1T19DAE/fwoFb3fOF3DUk8e37x3vN324tbhFAuT6lXXAOEwNdNaFndfO/NO0IA5VKCNTWGsmdq/W0/ligDewJutRC2SJ5lZe5kqLTMQK5Yq3Lg7vxeWz2nN1iLzutRXUa6K6KL5pAjVgfn3N5VC0lh7jmR8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=jJMKX5yr; arc=none smtp.client-ip=95.215.58.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="jJMKX5yr" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1780984976; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RGfvtqtSRbm7XGzyftXzdD+Hm1sGp6DXlZOLRoWzqRc=; b=jJMKX5yrw/cwx9QtPhqnZ+n4EiNXOfSqMtPQv9vMXU+DV9bi6XUTl5OK1b8ohNarRld1IE sXa6gXC3eAflOi3OUXWjKoQHHv67bsKv9GBRxlQ3aSCOh2qtyekJrVdpNWKeANP57GRRja QxltgqWzzUj1hjelrx9nKTbRhendWUE= From: Atish Patra Date: Mon, 08 Jun 2026 23:01:30 -0700 Subject: [PATCH v6 16/21] RISC-V: perf: Add legacy event encodings via sysfs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260608-counter_delegation-v6-16-285b72ed65a9@meta.com> References: <20260608-counter_delegation-v6-0-285b72ed65a9@meta.com> In-Reply-To: <20260608-counter_delegation-v6-0-285b72ed65a9@meta.com> To: James Clark , Rob Herring , Atish Patra , Arnaldo Carvalho de Melo , Jiri Olsa , Will Deacon , Mark Rutland , Anup Patel , Namhyung Kim , Paul Walmsley , Krzysztof Kozlowski , Ian Rogers Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Migadu-Flow: FLOW_OUT From: Atish Patra Define sysfs details for the legacy events so that any tool can parse these to understand the minimum set of legacy events supported by the platform. The sysfs entry will describe both event encoding and corresponding counter map so that an perf event can be programmed accordingly. Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 4b4f151a0744..00b84b28117a 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -130,7 +130,20 @@ static struct attribute_group riscv_cdeleg_pmu_format_group = { .attrs = riscv_cdeleg_pmu_formats_attr, }; +#define RVPMU_EVENT_ATTR_RESOLVE(m) #m +#define RVPMU_EVENT_CMASK_ATTR(_name, _var, config, mask) \ + PMU_EVENT_ATTR_STRING(_name, rvpmu_event_attr_##_var, \ + "event=" RVPMU_EVENT_ATTR_RESOLVE(config) \ + ",counterid_mask=" RVPMU_EVENT_ATTR_RESOLVE(mask)) + +#define RVPMU_EVENT_ATTR_PTR(name) (&rvpmu_event_attr_##name.attr.attr) + +static struct attribute_group riscv_cdeleg_pmu_event_group __ro_after_init = { + .name = "events", +}; + static const struct attribute_group *riscv_cdeleg_pmu_attr_groups[] = { + &riscv_cdeleg_pmu_event_group, &riscv_cdeleg_pmu_format_group, NULL, }; @@ -431,11 +444,14 @@ struct riscv_vendor_pmu_events { const struct riscv_pmu_event *hw_event_map; const struct riscv_pmu_event (*cache_event_map)[PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_RESULT_MAX]; + struct attribute **attrs_events; }; -#define RISCV_VENDOR_PMU_EVENTS(_vendorid, _archid, _implid, _hw_event_map, _cache_event_map) \ +#define RISCV_VENDOR_PMU_EVENTS(_vendorid, _archid, _implid, _hw_event_map, \ + _cache_event_map, _attrs) \ { .vendorid = _vendorid, .archid = _archid, .implid = _implid, \ - .hw_event_map = _hw_event_map, .cache_event_map = _cache_event_map }, + .hw_event_map = _hw_event_map, .cache_event_map = _cache_event_map, \ + .attrs_events = _attrs }, static struct riscv_vendor_pmu_events pmu_vendor_events_table[] = { }; @@ -457,6 +473,8 @@ static void rvpmu_vendor_register_events(void) pmu_vendor_events_table[i].archid == arch_id) { current_pmu_hw_event_map = pmu_vendor_events_table[i].hw_event_map; current_pmu_cache_event_map = pmu_vendor_events_table[i].cache_event_map; + riscv_cdeleg_pmu_event_group.attrs = + pmu_vendor_events_table[i].attrs_events; break; } } -- 2.53.0-Meta