From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-179.mta0.migadu.com (out-179.mta0.migadu.com [91.218.175.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3AD193CB2E5; Tue, 9 Jun 2026 06:01:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.179 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780984901; cv=none; b=T2fFlHyim9A6Au87qYcyzojJ/+3x6ibs2kEwjQo9giLxjkiYm0sXl4zk5HXiLJsS32bzAwkqwM2meFAi5Z/zeNJgX7/JUYVb15cw6dsYRJf4/Eklp5GaItirJgbAMHSTG4Mppvs5EXwhsNEfr41hgmv/vSZ81AydWRM6SeoqfmE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780984901; c=relaxed/simple; bh=Uy+6u+zVVnKDyhH828jdTZwad1FK1t8vFUHFHWkaisM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GMamlalffWg/3KmYg66wnrRdQIf70m5YCeyh84XtuLcde17M42sa7an4uc5iHCgpndfmnKT/25l9WGcoiRh+b+s1oxgePAGr3/DP0VyxQrxhUiETKUYO87FdqDpgoOv3oMvs++f2S4k2z5W8HHzb1e1NeLEz1OzTRQTWGLh1qQM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=sw3aDZVd; arc=none smtp.client-ip=91.218.175.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="sw3aDZVd" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1780984898; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UiQdcLZt3TDwJvzued5odyBBsjPd7XdI6I5xzQS3xEM=; b=sw3aDZVdPfe7llAGxyxlkoeaj+NZpqQ/1TJM1oDrs+kUR3wvHtJBHbN1vZstxRbklghJic rWrY5YxoeQ5ifGmmA6R1Nv+8t2fDwbJSDpCAFMwNpY8pxwetZhFooBdJ0YArhjPejNqGuh AwS5gfWT188HhM3CpvbwxQ+bkjvke7E= From: Atish Patra Date: Mon, 08 Jun 2026 23:01:17 -0700 Subject: [PATCH v6 03/21] dt-bindings: riscv: add Sxcsrind ISA extension description Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260608-counter_delegation-v6-3-285b72ed65a9@meta.com> References: <20260608-counter_delegation-v6-0-285b72ed65a9@meta.com> In-Reply-To: <20260608-counter_delegation-v6-0-285b72ed65a9@meta.com> To: James Clark , Rob Herring , Atish Patra , Arnaldo Carvalho de Melo , Jiri Olsa , Will Deacon , Mark Rutland , Anup Patel , Namhyung Kim , Paul Walmsley , Krzysztof Kozlowski , Ian Rogers Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Migadu-Flow: FLOW_OUT From: Atish Patra Add the S[m|s]csrind ISA extension description. Acked-by: Rob Herring (Arm) Signed-off-by: Atish Patra --- Documentation/devicetree/bindings/riscv/extensions.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 2b0a8a93bb21..4be557dc215d 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -181,6 +181,14 @@ properties: changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. + - const: smcsrind + description: | + The standard Smcsrind supervisor-level extension extends the + indirect CSR access mechanism defined by the Smaia extension. This + extension allows other ISA extension to use indirect CSR access + mechanism in M-mode as ratified in the 20240326 version of the + privileged ISA specification. + - const: smmpm description: | The standard Smmpm extension for M-mode pointer masking as @@ -199,6 +207,14 @@ properties: added by other RISC-V extensions in H/S/VS/U/VU modes and as ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable. + - const: sscsrind + description: | + The standard Sscsrind supervisor-level extension extends the + indirect CSR access mechanism defined by the Ssaia extension. This + extension allows other ISA extension to use indirect CSR access + mechanism in S-mode as ratified in the 20240326 version of the + privileged ISA specification. + - const: ssaia description: | The standard Ssaia supervisor-level extension for the advanced -- 2.53.0-Meta