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The panel's 40-pin connector allows it to be directly connected to i.MX93 11x11 EVK board. Link: https://www.nxp.com/design/design-center/development-boards-and-designs/dy1212w-4856-tft-lcd-panel-with-lvds-interface:DY1212W-4856 [1] Signed-off-by: Liu Ying --- arch/arm64/boot/dts/freescale/Makefile | 4 ++ .../freescale/imx93-11x11-evk-dy1212w-4856.dtso | 81 ++++++++++++++++++++++ 2 files changed, 85 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 8ddaab127ab9..dbe27d757c86 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -588,6 +588,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-ontat-kd50g21-40nt-a1.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-tianma-tm050rdh03.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb + +imx93-11x11-evk-dy1212w-4856-dtbs += imx93-11x11-evk.dtb imx93-11x11-evk-dy1212w-4856.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk-dy1212w-4856.dtb + dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-frdm.dtb imx93-11x11-frdm-pixpaper-dtbs += imx93-11x11-frdm.dtb imx93-11x11-frdm-pixpaper.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk-dy1212w-4856.dtso b/arch/arm64/boot/dts/freescale/imx93-11x11-evk-dy1212w-4856.dtso new file mode 100644 index 000000000000..35f7c5699e3a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk-dy1212w-4856.dtso @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 NXP + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + panel-lvds { + compatible = "boe,ev121wxm-n10-1850"; + backlight = <&backlight_lvds>; + power-supply = <&buck4>; + + panel-timing { + /* + * Set clock frequency to 71142858Hz to accommodate + * IMX93_CLK_VIDEO_PLL rate at 498000000Hz in a rate + * table. + */ + clock-frequency = <71142858>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <48>; + hback-porch = <80>; + hsync-len = <32>; + vfront-porch = <3>; + vback-porch = <14>; + vsync-len = <6>; + }; + + port { + panel_lvds_in: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; +}; + +&backlight_lvds { + status = "okay"; +}; + +&lcdif { + status = "okay"; +}; + +&lvds_bridge { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + ldb_lvds_ch0: endpoint { + remote-endpoint = <&panel_lvds_in>; + }; + }; + }; +}; + +&media_blk_ctrl { + assigned-clocks = <&clk IMX93_CLK_MEDIA_AXI>, + <&clk IMX93_CLK_MEDIA_APB>, + <&clk IMX93_CLK_MEDIA_DISP_PIX>, + <&clk IMX93_CLK_VIDEO_PLL>; + assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>, + <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, + <&clk IMX93_CLK_VIDEO_PLL>; + /* + * Set IMX93_CLK_MEDIA_DISP_PIX rate to 71142858Hz to accommodate + * IMX93_CLK_VIDEO_PLL rate at 498000000Hz in a rate table. + */ + assigned-clock-rates = <400000000>, <133333333>, <71142858>, <498000000>; + status = "okay"; +}; -- 2.43.0