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Sun, 07 Jun 2026 21:17:00 -0700 (PDT) Received: from hu-neersoni-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c16649fcdfsm209392525ad.78.2026.06.07.21.16.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Jun 2026 21:17:00 -0700 (PDT) From: Neeraj Soni To: ulf.hansson@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, neeraj.soni@oss.qualcomm.com, Abel Vesa , Abhinaba Rakshit , Kuldeep Singh , Krzysztof Kozlowski Subject: [PATCH v7 1/3] dt-bindings: mmc: sdhci-msm: Add ICE phandle Date: Mon, 8 Jun 2026 09:46:48 +0530 Message-Id: <20260608041650.541502-2-neeraj.soni@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260608041650.541502-1-neeraj.soni@oss.qualcomm.com> References: <20260608041650.541502-1-neeraj.soni@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: rhDFIdFJAyEb9OOOTOxaDILwJFzJcZIV X-Proofpoint-GUID: rhDFIdFJAyEb9OOOTOxaDILwJFzJcZIV X-Authority-Analysis: v=2.4 cv=YIWvDxGx c=1 sm=1 tr=0 ts=6a26423e cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=kJ_adD4HZfoOqhAMuKMA:9 a=324X-CrmTo6CU4MGRt3R:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA4MDAzNCBTYWx0ZWRfXwT4F8d/ZRXIY gTA1Ha7fxsKAqkDTOocBOg9JNMIVxNXP2LPqZmaC9zLwjUO2zUN2AC70WhRmu9+EZkhmxHfP+Vk h6UZ+I/W8O6LrmnIb5fspwfiT3xJuV9b5PaXT6JxXKOub+X7eKz9XpABhk+M8HoGjinXPwiR2+5 s+Qzl9w/MM7YB458Msr0Mtx+6UdqAb2ln48xJewf90dOd2DzYYXhHzMQfdeLzbmf2ESxcCKGmu+ 05Si5K7zg2rR+rUdmLIC7OX70rWEQE6iIJkYssRPZ8Wds+XgWcsnqpiOCM5LdJ+jHHw8YaVqTZa zKhqWr+libl9Li/t0v6lxztQHiVHWJU8bNiHkzA+lddzN5Kafh7FjhsnycVss7U9tcRSdE3bhOu lCaAfHpCz8MmvrAZhoPaI3l1jZUWGOwcUb3+Zm6TY9r8YO5T30mXJm92OCFnDMblwTFJD/Z7ETx 9tGoykgMeBerkYWiGrQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-08_01,2026-06-05_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 spamscore=0 phishscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606080034 Starting with sc7280(kodiak), the ICE will have its own device-tree node. So add the qcom,ice property to reference it. To avoid double-modeling, when qcom,ice is present, disallow an embedded ICE register region in the SDHCI node. Older SoCs without ICE remain valid as no additional requirement is imposed. Co-developed-by: Abel Vesa Signed-off-by: Abel Vesa Co-developed-by: Abhinaba Rakshit Signed-off-by: Abhinaba Rakshit Reviewed-by: Kuldeep Singh Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20260310113557.348502-2-neeraj.soni@oss.qualcomm.com Signed-off-by: Neeraj Soni --- .../bindings/mmc/qcom,sdhci-msm.yaml | 95 +++++++++++++------ 1 file changed, 67 insertions(+), 28 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml index bd558a11b792..b3fcc1673c10 100644 --- a/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml @@ -145,6 +145,11 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: platform specific settings for DLL_CONFIG reg. + qcom,ice: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the Inline Crypto Engine (ICE) hardware block for this controller. + iommus: minItems: 1 maxItems: 8 @@ -198,35 +203,69 @@ allOf: enum: - qcom,sdhci-msm-v4 then: - properties: - reg: - minItems: 2 - items: - - description: Host controller register map - - description: SD Core register map - - description: CQE register map - - description: Inline Crypto Engine register map - reg-names: - minItems: 2 - items: - - const: hc - - const: core - - const: cqhci - - const: ice + if: + required: + - qcom,ice + then: + properties: + reg: + minItems: 2 + items: + - description: Host controller register map + - description: SD Core register map + - description: CQE register map + reg-names: + minItems: 2 + items: + - const: hc + - const: core + - const: cqhci + else: + properties: + reg: + minItems: 2 + items: + - description: Host controller register map + - description: SD Core register map + - description: CQE register map + - description: Inline Crypto Engine register map + reg-names: + minItems: 2 + items: + - const: hc + - const: core + - const: cqhci + - const: ice else: - properties: - reg: - minItems: 1 - items: - - description: Host controller register map - - description: CQE register map - - description: Inline Crypto Engine register map - reg-names: - minItems: 1 - items: - - const: hc - - const: cqhci - - const: ice + if: + required: + - qcom,ice + then: + properties: + reg: + minItems: 1 + items: + - description: Host controller register map + - description: CQE register map + reg-names: + minItems: 1 + items: + - const: hc + - const: cqhci + else: + properties: + reg: + minItems: 1 + items: + - description: Host controller register map + - description: CQE register map + - description: Inline Crypto Engine register map + reg-names: + minItems: 1 + items: + - const: hc + - const: cqhci + - const: ice unevaluatedProperties: false -- 2.34.1