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Mon, 8 Jun 2026 09:29:09 -0500 Received: from ws.dhcp.ti.com (ws.dhcp.ti.com [172.24.233.149]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 658ET2bD3251356; Mon, 8 Jun 2026 09:29:06 -0500 From: Rishikesh Donadkar To: CC: , , , , , , , , Subject: [PATCH 1/4] media: i2c: ds90ub960: Enable CSI TX1 port Date: Mon, 8 Jun 2026 19:58:58 +0530 Message-ID: <20260608142901.3971821-2-r-donadkar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260608142901.3971821-1-r-donadkar@ti.com> References: <20260608142901.3971821-1-r-donadkar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA4C:EE_|SA2PR10MB4521:EE_ X-MS-Office365-Filtering-Correlation-Id: 3a6f9849-1b00-4ac5-e4f7-08dec56a4de9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|82310400026|376014|3023799007|56012099006|6133799003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: enGb601N5W/sV6ZHazaLoyNY1IIqwpBDupEL1lQQfDpc9rxYOo7+ldO0bbxHWRlwNrCQSir5ZBF7aYa5sCJIprrb/Kt0uuAhLUENPDE4oOMK6l1btzjX3AfmmNcOzz9eiQeGQCE/W6La3/ZX0prgw1F6u92ZTXtGqLf0NKb6GCYIQbI34c8UdMj2oGKi4TpixNU0gJWfv8L1pQ33WtazVg7UiDybdMyYCfdZF14bUC12/fi4qraZauwKbD9i/cI+l/UhaVF9+iDrguI8rXLfZfwBriPK+UemZKjFUKcizY8fmrmavVi6ZnqhFWQ9E8LhOr64AqFCmlIgyDYzua4tmllezAxnloGAeGzztyy6iS63DVJHoCUeZIxNSrKqNg+uGUUvDZBD0kpGpPs4QyOB3oOuME46Kh9zxbsYbUxTr/H6bKYHjuGvpb/lCKy/imPk X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jun 2026 14:29:09.6891 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3a6f9849-1b00-4ac5-e4f7-08dec56a4de9 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.194];Helo=[lewvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA2PR10MB4521 From: Yemike Abhilash Chandra The DS90UB960 chip has two CSI-2 transmit ports (TX0 and TX1), but the current driver implementation only utilizes TX0. To enable TX1 as the active output port, the I2C Bidirectional Control Channel (BCC) mapping in the RX_PORT_CTL register must be configured to use I2C Slave Port 1. This patch adds a new function, ub960_parse_active_ports(), which is called during driver initialization to scan the device tree and identify which RX and TX ports are enabled. The function creates bitmasks representing the active ports and uses these masks to correctly configure the RX_PORT_CTL register, ensuring proper port routing for whichever TX port is in use. DS90UB960 data sheet: https://www.ti.com/lit/ds/symlink/ds90ub960-q1.pdf Signed-off-by: Yemike Abhilash Chandra Co-developed-by: Rishikesh Donadkar Signed-off-by: Rishikesh Donadkar --- drivers/media/i2c/ds90ub960.c | 46 ++++++++++++++++++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/drivers/media/i2c/ds90ub960.c b/drivers/media/i2c/ds90ub960.c index 15a9797b47ac..653dc7a4eee5 100644 --- a/drivers/media/i2c/ds90ub960.c +++ b/drivers/media/i2c/ds90ub960.c @@ -26,6 +26,7 @@ * - i2c-atr could be made embeddable instead of allocatable. */ +#include #include #include #include @@ -76,6 +77,8 @@ #define UB960_NUM_BC_GPIOS 4 +#define UB960_CSI_TX0 BIT(4) + /* * Register map * @@ -114,6 +117,7 @@ #define UB960_SR_SCL_HIGH_TIME 0x0a #define UB960_SR_SCL_LOW_TIME 0x0b #define UB960_SR_RX_PORT_CTL 0x0c +#define UB960_SR_RX_PORT_CTL_BCC_MAP GENMASK(7, 4) #define UB960_SR_IO_CTL 0x0d #define UB960_SR_GPIO_PIN_STS 0x0e #define UB960_SR_GPIO_INPUT_CTL 0x0f @@ -589,6 +593,9 @@ struct ub960_data { u32 tx_data_rate; /* Nominal data rate (Gb/s) */ s64 tx_link_freq[1]; + u8 rx_mask; + u8 tx_mask; + struct i2c_atr *atr; struct { @@ -2538,7 +2545,18 @@ static int ub960_init_rx_ports_ub960(struct ub960_data *priv) struct device *dev = &priv->client->dev; unsigned int port_lock_mask; unsigned int port_mask; - int ret; + u8 enabled_rxports_mask; + u8 enabled_rxports; + int ret = 0; + + /* Configure I2C interface for RX ports */ + enabled_rxports_mask = FIELD_PREP(UB960_SR_RX_PORT_CTL_BCC_MAP, priv->rx_mask); + enabled_rxports = (priv->tx_mask & UB960_CSI_TX0) ? 0x00 : enabled_rxports_mask; + + ret = ub960_update_bits(priv, UB960_SR_RX_PORT_CTL, enabled_rxports_mask, + enabled_rxports, &ret); + if (ret) + return ret; for_each_active_rxport(priv, it) { ret = ub960_init_rx_port_ub960(priv, it.rxport); @@ -4789,6 +4807,30 @@ static int ub960_parse_dt_txports(struct ub960_data *priv) return 0; } +static void ub960_parse_active_ports(struct ub960_data *priv) +{ + struct device *dev = &priv->client->dev; + int nport; + + priv->rx_mask = 0; + priv->tx_mask = 0; + + for (nport = 0; nport < priv->hw_data->num_rxports + priv->hw_data->num_txports; nport++) { + struct fwnode_handle *ep_fwnode; + + ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), nport, 0, 0); + if (!ep_fwnode) + continue; + + if (nport < priv->hw_data->num_rxports) + priv->rx_mask |= BIT(nport); + else + priv->tx_mask |= BIT(nport); + + fwnode_handle_put(ep_fwnode); + } +} + static int ub960_parse_dt(struct ub960_data *priv) { int ret; @@ -5162,6 +5204,8 @@ static int ub960_probe(struct i2c_client *client) if (ret) goto err_mutex_destroy; + ub960_parse_active_ports(priv); + ret = ub960_parse_dt(priv); if (ret) goto err_disable_core_hw; -- 2.34.1