From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0CFA277C81 for ; Mon, 8 Jun 2026 13:32:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780925574; cv=none; b=INsgV0Tsu9XKBYWnM/p3kzbxV3fYf9+osLiis8hp3mht8jFxgIAuMpHypTl/ZF2NLESkLuOxaumvNIeEdceUyhR35dTfNmPthr/1exDSdkwFadq0dkXl5OLSgoozro0Aq+8H6h7PNkVI1YadP9mgIxxWVMkoBLr+Dt80Rlch/E0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780925574; c=relaxed/simple; bh=qcxaRvl4I1a8Mo0iiXNigHYsU7ODQZ9ywjgz5bodr6w=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Dsy9Mu9DVK2Lx3Ql7BTnBEdGUKjDmgt5r+jmz5AMEU+tCJwW7S/lyixWHkyn4rOyPBH8QC7uKjpGT6gQeM5PLjxOdL0hMxNLg2l3mbiTEoFliegU27KgN/889UB2bJfpANJ6kQNQ/Jycv0Zlh/kE1eJaaI61lRYUfacDlFBHk5Q= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=alTgc3IJ; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="alTgc3IJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1780925571; bh=qcxaRvl4I1a8Mo0iiXNigHYsU7ODQZ9ywjgz5bodr6w=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=alTgc3IJBVuI8iwVkVIZSWcP65Fhi0H1RopWa+2OrPm0WtG1pmc2tGpT8ciH9qwXb GDwPwJ1oVN+N48OV3cMUKfAgT+mDiogicULq6iB3T0xSsvU2haOnA4M2ASt5A+77BX sL9LTfNaIC1mCR0lmWZR7wQg4M5lRLVfUI4fWs6l1/zV4WQfRKgBoYL/zZfP+IrbMZ oeQ/0tGPRh7EDjG+v9K3cIrs/t+6RiH/v5hxSni0bwbXQTyh7iu+tyU7psM7tahSQ0 CI/XhqGfTpD/SFjfA5FiCnFtKyjNyNFJrFfUUO02xbL3s94T4tgU4AlVu5LT4FTGZO T+3UelkHS5dNQ== Received: from fedora-2.home (unknown [100.64.0.11]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: bbrezillon) by bali.collaboradmins.com (Postfix) with ESMTPSA id B269E17E0191; Mon, 8 Jun 2026 15:32:50 +0200 (CEST) Date: Mon, 8 Jun 2026 15:32:46 +0200 From: Boris Brezillon To: Karunika Choo Cc: dri-devel@lists.freedesktop.org, nd@arm.com, Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH 05/18] drm/panthor: Move register base offsets to the HW description Message-ID: <20260608153246.5fdbea05@fedora-2.home> In-Reply-To: <20260528150546.3168527-6-karunika.choo@arm.com> References: <20260528150546.3168527-1-karunika.choo@arm.com> <20260528150546.3168527-6-karunika.choo@arm.com> Organization: Collabora X-Mailer: Claws Mail 4.4.0 (GTK 3.24.52; x86_64-redhat-linux-gnu) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Thu, 28 May 2026 16:05:33 +0100 Karunika Choo wrote: > /** > * struct panthor_hw - GPU specific register mapping and functions > */ > struct panthor_hw { > - /** @features: Bitmap containing panthor_hw_feature */ > - > /** @ops: Panthor HW specific operations */ > struct panthor_hw_ops ops; > + > + /** @map: Panthor HW-specific register base addresses */ > + struct panthor_hw_regmap map; map is a bit too vague. Can we rename this regbank_offsets or something along those lines? If we do that, we can drop the _base in the field names, because it'd be obvious that these are offsets when the field is used: void __iomem *gpu_iomem = ptdev->iomem + ptdev->hw->regbank_offsets.gpu_control; > }; >