From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 960DC382296 for ; Mon, 8 Jun 2026 13:41:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780926078; cv=none; b=Smf8B10f9Nmanp/CXlOpdry4U7S2PiGYa2F3hvp3ulMvpGz5pCfQn370eCQFrSycreJiDSPJvlGBRrwkJrAD6JsUy3qvKq2O6qDMr+yX5LJpKegmy8w9Cprld1LKsldZbbhZ+MYW3NT8IU5y9Iy/2fMgSZ43+CtOoKtnvJOsh/Q= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780926078; c=relaxed/simple; bh=hyDWsynSVBRtilr2H+1tPwAl4HIuL+CLETu8CEJKbzo=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nyaZP1CTfOfOF4QdcDjYulO0fiL/zHVd+7c4tzIr7f9jNvC2AXks21g7IUDSGi2R56eMdXF8SI3kb063I0QTVZ907JXBKFfJMIlZW1dP0Lgc5C+r/seM0fgJ6MZlLQdPR/BQISB9tSek/HBb8Soa049YK/cCRBQza0iqKwT/c4w= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=hrvE/h6Z; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="hrvE/h6Z" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1780926075; bh=hyDWsynSVBRtilr2H+1tPwAl4HIuL+CLETu8CEJKbzo=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=hrvE/h6ZYOFBJ1cv8hNMy2gnfB++EurkblbweqakrDfcBVEqV0uRNEymZ5V51wpgQ 98vyXoVoVVQRGu3JnFZYTjP7JyiStgYGKz/ZoiDabKRzWce6Miogqd7vJtaMxvG37A wSCpAgxHEj8hQvviWnpOYczigmwnsnootg5c4io/x1DaLymuQLDZgUhWAuRkJ/GNw0 Ll5B/2l+CphLn5O+zcrzo2Y8fp1Etw4Lswlrg4ZxgWHaAc4j2jhT7zPWHpevcDG7r4 fDkaOtIIaC5RzB4c1YhryzWpBpZIZ/UkzU7cEd1oFq2J8CtjbeU9+AikEKEZAoh+6C bf4Bxgb6hmbzQ== Received: from fedora-2.home (unknown [100.64.0.11]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: bbrezillon) by bali.collaboradmins.com (Postfix) with ESMTPSA id 6BDAD17E062B; Mon, 8 Jun 2026 15:41:15 +0200 (CEST) Date: Mon, 8 Jun 2026 15:41:01 +0200 From: Boris Brezillon To: Karunika Choo Cc: dri-devel@lists.freedesktop.org, nd@arm.com, Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH 05/18] drm/panthor: Move register base offsets to the HW description Message-ID: <20260608154101.2460796f@fedora-2.home> In-Reply-To: <20260608153246.5fdbea05@fedora-2.home> References: <20260528150546.3168527-1-karunika.choo@arm.com> <20260528150546.3168527-6-karunika.choo@arm.com> <20260608153246.5fdbea05@fedora-2.home> Organization: Collabora X-Mailer: Claws Mail 4.4.0 (GTK 3.24.52; x86_64-redhat-linux-gnu) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Mon, 8 Jun 2026 15:32:46 +0200 Boris Brezillon wrote: > On Thu, 28 May 2026 16:05:33 +0100 > Karunika Choo wrote: > > > /** > > * struct panthor_hw - GPU specific register mapping and functions > > */ > > struct panthor_hw { > > - /** @features: Bitmap containing panthor_hw_feature */ > > - > > /** @ops: Panthor HW specific operations */ > > struct panthor_hw_ops ops; > > + > > + /** @map: Panthor HW-specific register base addresses */ > > + struct panthor_hw_regmap map; > > map is a bit too vague. Can we rename this regbank_offsets or something > along those lines? If we do that, we can drop the _base in the field > names, because it'd be obvious that these are offsets when the field is > used: > > void __iomem *gpu_iomem = ptdev->iomem + ptdev->hw->regbank_offsets.gpu_control; Actually, MMU ranges need a stride, so I'd go for: struct panthor_regbank { u32 offset; u32 stride; }; struct panthor_regs_layout { struct panthor_regbank gpu_control; struct panthor_regbank pwr_control; .. }; struct panthor_hw { struct panthor_regs_layout regs_layout; }; > > > }; > >