From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92D18383C99 for ; Mon, 8 Jun 2026 13:59:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780927183; cv=none; b=fMzHufoqVrOJyAnCMqobiDRPyy2bPmMLJIzFu7EeMgIIPof6fJTg7a3sG80G3Nved6nrbz4nVEC2WMqNOMM/8FSAwPp6w+ATrJgShN5rIeDx6cobre77d67NzIAxTxBaUk8xy3b6AhGZi9cv6yTtauMaenwFJAh14Fh9aMfRMFY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780927183; c=relaxed/simple; bh=4KVrLMycKsikXvnvino2QPXXCvoymR4yiO89X6KtzAA=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JYYeu8KeZcetXINmZDvxcFMOboenKPVo270Q+5kZUOc6Jlav90Xjb1mwhFmSCXz3fWkltWlW6K7fW1h/I+u380y9jb/ij2JXQeAjvWE4SeStjf4KpmuPDZh3oLFqg34CuZEz48h7dD3jiOblrm0WRLdbGtR3TVQJ5nwwstLZcN0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=Y/Mbym9N; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="Y/Mbym9N" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1780927180; bh=4KVrLMycKsikXvnvino2QPXXCvoymR4yiO89X6KtzAA=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=Y/Mbym9NKFHUwPhlbJjf7kZd1EdatfkyAgNmRTqXEfg94CAq33no/JgtljslZgNNf vU2LbPE+DZZe4qD8Y2NYO6ojDrKEsSb9dJYbDJcDU+k8YW8TNqdWjNoNmFomKLLEj/ MSOdk1XQJ/mJUIpzn701m47kvI8ZWZWk3D7wkO0RFmDf/OgSguLbJk5zc+bP9lTNYj UXyvTRdWRROcXrUZtMPHMoLCJldPO/xw8Fs65nvYt2bqkcLeJVKL/nTk0oKdlllgQZ Fpj/AMt4ZqT9LXKl3aNj/0ZQIvTsRCtSYAxNanzdLCqxt6H1AZAG9IIeVF02bPbIcy XWAbjNF+9qZ9Q== Received: from fedora-2.home (unknown [100.64.0.11]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: bbrezillon) by bali.collaboradmins.com (Postfix) with ESMTPSA id 681CD17E0416; Mon, 8 Jun 2026 15:59:40 +0200 (CEST) Date: Mon, 8 Jun 2026 15:59:33 +0200 From: Boris Brezillon To: Karunika Choo Cc: dri-devel@lists.freedesktop.org, nd@arm.com, Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH 07/18] drm/panthor: Add Mali v15 hardware support Message-ID: <20260608155933.080e73b3@fedora-2.home> In-Reply-To: <20260528150546.3168527-8-karunika.choo@arm.com> References: <20260528150546.3168527-1-karunika.choo@arm.com> <20260528150546.3168527-8-karunika.choo@arm.com> Organization: Collabora X-Mailer: Claws Mail 4.4.0 (GTK 3.24.52; x86_64-redhat-linux-gnu) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Thu, 28 May 2026 16:05:35 +0100 Karunika Choo wrote: > @@ -251,12 +279,56 @@ static int panthor_gpu_info_init(struct panthor_device *ptdev) > ptdev->gpu_info.tiler_present = gpu_read64(gpu_iomem, GPU_TILER_PRESENT); > ptdev->gpu_info.l2_present = gpu_read64(gpu_iomem, GPU_L2_PRESENT); > } > +} > + > +static void panthor_gpu_info_v15_init(struct panthor_device *ptdev) > +{ > + void __iomem *pwr_iomem = ptdev->iomem + ptdev->hw->map.pwr_control_base; > + u64 texture_features; > + > + ptdev->gpu_info.gpu_rev_wide = gpu_read64(ptdev->iomem, DISCOVER_REVIDR); > + ptdev->gpu_info.l2_features_wide = gpu_read64(ptdev->iomem, DISCOVER_L2_FEATURES); > + > + texture_features = gpu_read64(ptdev->iomem, DISCOVER_TEXTURE_FEATURES); > + ptdev->gpu_info.texture_features[0] = lower_32_bits(texture_features); > + ptdev->gpu_info.texture_features[1] = upper_32_bits(texture_features); > + > + ptdev->gpu_info.thread_features = gpu_read(ptdev->iomem, DISCOVER_THREAD_FEATURES); > + ptdev->gpu_info.max_threads = gpu_read(ptdev->iomem, DISCOVER_THREAD_MAX_THREADS); > + ptdev->gpu_info.thread_num_active_granularity = > + gpu_read(ptdev->iomem, DISCOVER_THREAD_NUM_ACTIVE_GRANULARITY); > + > + ptdev->gpu_info.gpu_features = gpu_read64(ptdev->iomem, DISCOVER_GPU_FEATURES); > + > + /* The following _HI registers do not contain any information (yet) */ AFAICT, this is also the case for DISCOVER_GPU_FEATURES. > + ptdev->gpu_info.mem_features = gpu_read(ptdev->iomem, DISCOVER_MEM_FEATURES); > + ptdev->gpu_info.mmu_features = gpu_read(ptdev->iomem, DISCOVER_MMU_FEATURES); > + ptdev->gpu_info.coherency_features = gpu_read(ptdev->iomem, DISCOVER_AMBA_FEATURES); > + ptdev->gpu_info.tiler_features = gpu_read(ptdev->iomem, DISCOVER_TILER_FEATURES); > + ptdev->gpu_info.core_features = gpu_read(ptdev->iomem, DISCOVER_CORE_FEATURES); > + > + /* AS_PRESENT register removed on v15+ create virtual mask from MMU_FEATURES.AS_COUNT */ > + ptdev->gpu_info.as_present = > + (1U << MMU_FEATURES_AS_COUNT(ptdev->gpu_info.mmu_features)) - 1; > + > + ptdev->gpu_info.l2_present = gpu_read64(pwr_iomem, PWR_L2_PRESENT); > + ptdev->gpu_info.tiler_present = gpu_read64(pwr_iomem, PWR_TILER_PRESENT); > + ptdev->gpu_info.shader_present = gpu_read64(pwr_iomem, PWR_SHADER_PRESENT); > +}