From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CBE9313520; Tue, 9 Jun 2026 10:13:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780999993; cv=none; b=l8PZTg2G0OAW+ZOPLAadGSZTeTv0HoRYyJ6Kr+INCBjaw7huiQ0KIWBLIhSNOlTkk839C/3o3KUJDRN/il+2RyrSnAUxWQK8cnPDJab69XH0DhvlDxt5LewPWGzY/1ipzd+8WdXhAy4wTiap4n/vKMFgllzQk0CCv0FygLkJc4E= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780999993; c=relaxed/simple; bh=nRHCqNHCFawd3UDkIf/Ho0VBsSH2kvnFFttYhBUHJRQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NbGAv6oAZV7ukFNAz1GBKkFkhDai8SRYwdwfMIpDAPhJbxixekK/iWjP+ZtPMkc6rMJYWMTu/lWRLxq3aMEf+n7XiXE2RLh3jKjeNmBanfz8neaRZsQOwtq7gl43uiLr4CG6n9FrqXUX//sDMxgZL4ITvVsFxVwzckvXlxMorME= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bQcIiU2Z; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bQcIiU2Z" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1923DC2BCC7; Tue, 9 Jun 2026 10:13:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1780999993; bh=nRHCqNHCFawd3UDkIf/Ho0VBsSH2kvnFFttYhBUHJRQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=bQcIiU2ZZTVC0vaiKxxh6fexkRfu7jL4IXidLa97SZMZjEKHyaGUw0dOv0qBl156B tC1DGobZBjXKo7lLMvgumtwImVRHUc5ZcxogXKeM9bmOIl1ksuh9hy5CxX4H1VyKLN qKnuJ1S8sKl5S1gnxubS16M9eeJiUqQNV+Avhjb8qMTsqdgNtB0N47fHMgLms6z/RI dkAJZwbSgmlqZGW6nb81YW6uh1oFPRwOxO8I4GBMha/NBtgvcgDWqhesuIVxlRCYig SEFrpWSVQEKZhifn/8qagemN2IyYeCgGSjPMm72RGQHTBZpI6L1vrNagzbeayI7ip0 v8CKAVG//wYMw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id F23E4CD8CAA; Tue, 9 Jun 2026 10:13:12 +0000 (UTC) From: Rodrigo Alencar via B4 Relay Date: Tue, 09 Jun 2026 11:13:05 +0100 Subject: [PATCH v2 10/12] iio: dac: ad5686: add triggered buffer support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260609-ad5686-new-features-v2-10-70b423f5c76d@analog.com> References: <20260609-ad5686-new-features-v2-0-70b423f5c76d@analog.com> In-Reply-To: <20260609-ad5686-new-features-v2-0-70b423f5c76d@analog.com> To: Michael Auchter , linux@analog.com, linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org Cc: Michael Hennerich , Jonathan Cameron , David Lechner , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Kees Cook , "Gustavo A. R. Silva" , Rodrigo Alencar X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1780999989; l=3826; i=rodrigo.alencar@analog.com; s=default; h=from:subject:message-id; bh=hsVYPXQq0b3tZZCpLsHTxe6Z4HlqV/AfUr5zyAZBrds=; b=lLfOweS8HhPCS45Uy8qJhAEV05r/FKaEn4o4VW/VfyOFF2zarSW5RbrXsph3Wq035tDJ1k9SL E8rVMC8mDM4CeGFXZNqVM0uXo6nSi1QoDGYc/fHZKh4XYwPOkxNFNnN X-Developer-Key: i=rodrigo.alencar@analog.com; a=ed25519; pk=ULeHbgU/OYh/PG/4anHDfLgldFItQHAhOktYRVLMFRo= X-Endpoint-Received: by B4 Relay for rodrigo.alencar@analog.com/default with auth_id=561 X-Original-From: Rodrigo Alencar Reply-To: rodrigo.alencar@analog.com From: Rodrigo Alencar Implement trigger handler by leveraging the LDAC gpio to update all DAC channels at once when it is available. Also, the multiple channel writes can be flushed at once with the sync() operation. Signed-off-by: Rodrigo Alencar --- drivers/iio/dac/Kconfig | 2 ++ drivers/iio/dac/ad5686.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/drivers/iio/dac/Kconfig b/drivers/iio/dac/Kconfig index 657c68e75542..5f14fcd780e2 100644 --- a/drivers/iio/dac/Kconfig +++ b/drivers/iio/dac/Kconfig @@ -240,6 +240,8 @@ config LTC2688 config AD5686 tristate + select IIO_BUFFER + select IIO_TRIGGERED_BUFFER config AD5686_SPI tristate "Analog Devices AD5686 and similar multi-channel DACs (SPI)" diff --git a/drivers/iio/dac/ad5686.c b/drivers/iio/dac/ad5686.c index 4243d8052550..487c61fbe5ab 100644 --- a/drivers/iio/dac/ad5686.c +++ b/drivers/iio/dac/ad5686.c @@ -20,7 +20,11 @@ #include #include +#include #include +#include +#include +#include #include "ad5686.h" @@ -246,6 +250,7 @@ static const struct iio_chan_spec_ext_info ad5686_ext_info[] = { .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),\ .address = addr, \ + .scan_index = chan, \ .scan_type = { \ .sign = 'u', \ .realbits = (bits), \ @@ -470,6 +475,60 @@ const struct ad5686_chip_info ad5679r_chip_info = { }; EXPORT_SYMBOL_NS_GPL(ad5679r_chip_info, "IIO_AD5686"); +static irqreturn_t ad5686_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf = p; + struct iio_dev *indio_dev = pf->indio_dev; + struct iio_buffer *buffer = indio_dev->buffer; + struct ad5686_state *st = iio_priv(indio_dev); + u16 val[AD5686_MAX_CHANNELS] = { }; + unsigned int scan_count; + int ret, ch, i = 0; + bool async_update; + u8 cmd; + + ret = iio_pop_from_buffer(buffer, val); + if (ret) + goto out_notify_done; + + mutex_lock(&st->lock); + + scan_count = bitmap_weight(indio_dev->active_scan_mask, + iio_get_masklength(indio_dev)); + async_update = st->ldac_gpio && scan_count > 1; + if (async_update) { + /* use LDAC to update all channels simultaneously */ + cmd = AD5686_CMD_WRITE_INPUT_N; + gpiod_set_value_cansleep(st->ldac_gpio, 0); + } else { + cmd = AD5686_CMD_WRITE_INPUT_N_UPDATE_N; + } + + iio_for_each_active_channel(indio_dev, ch) { + ret = st->ops->write(st, cmd, indio_dev->channels[ch].address, val[i++]); + if (ret) + break; + } + + /* + * If sync() is available, it is called here regardless of write + * failure to allow bus implementation to reset. In that case, partial + * writes are unlikely as the write operations would just queue up + * the transfers. + */ + if (st->ops->sync) + ret = st->ops->sync(st); /* flush all pending transfers */ + + if (async_update) + gpiod_set_value_cansleep(st->ldac_gpio, 1); + + mutex_unlock(&st->lock); +out_notify_done: + iio_trigger_notify_done(indio_dev->trig); + + return IRQ_HANDLED; +} + int ad5686_probe(struct device *dev, const struct ad5686_chip_info *chip_info, const char *name, const struct ad5686_bus_ops *ops, @@ -569,6 +628,13 @@ int ad5686_probe(struct device *dev, return -EINVAL; } + ret = devm_iio_triggered_buffer_setup_ext(dev, indio_dev, NULL, + &ad5686_trigger_handler, + IIO_BUFFER_DIRECTION_OUT, + NULL, NULL); + if (ret) + return ret; + return devm_iio_device_register(dev, indio_dev); } EXPORT_SYMBOL_NS_GPL(ad5686_probe, "IIO_AD5686"); -- 2.43.0