From: Breno Leitao <leitao@debian.org>
To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Danilo Krummrich <dakr@kernel.org>,
Sudeep Holla <sudeep.holla@kernel.org>,
Pierre Gondois <pierre.gondois@arm.com>
Cc: driver-core@lists.linux.dev, linux-kernel@vger.kernel.org,
kernel-team@meta.com, Breno Leitao <leitao@debian.org>
Subject: [PATCH] cacheinfo: don't propagate DT/ACPI error when arch supplies info (arm64)
Date: Tue, 09 Jun 2026 09:23:53 -0700 [thread overview]
Message-ID: <20260609-cacheinfo-v1-1-35864c9a8f0c@debian.org> (raw)
cache_setup_properties() sets use_arch_info = true when DT/ACPI
provide no cache nodes and the arch can derive the topology from
CPU registers (e.g. arm64 reading CLIDR_EL1), but still returns the
original -ENOENT. cache_shared_cpu_map_setup() bails on that error
before the new flag can take effect, so the first CPU brought online
always trips a misleading warning:
cacheinfo: Unable to detect cache hierarchy for CPU 0
Subsequent CPUs skip cache_setup_properties() entirely because
use_arch_info is now true, which is why only CPU0 hits it. This is
reproducible on arm64 with the QEMU 'virt' machine, whose default DT
has no cache nodes.
Clear ret after setting use_arch_info so the caller proceeds and
populates the shared cpu map via the arch-supplied leaves.
Fixes: ef9f643a9f8b ("cacheinfo: Add use_arch[|_cache]_info field/function")
Signed-off-by: Breno Leitao <leitao@debian.org>
---
Cc; hruben@meta.com
---
drivers/base/cacheinfo.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index 70701d3bc81c..4e11d36f127e 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
@@ -401,9 +401,18 @@ static int cache_setup_properties(unsigned int cpu)
else if (!acpi_disabled)
ret = cache_setup_acpi(cpu);
- // Assume there is no cache information available in DT/ACPI from now.
- if (ret && use_arch_cache_info())
+ /*
+ * If DT/ACPI lacks cache nodes but the arch can derive the topology
+ * from CPU registers (e.g. arm64 reading CLIDR_EL1), fall back to
+ * that path instead of propagating the error. Otherwise the very
+ * first CPU processed trips a misleading "Unable to detect cache
+ * hierarchy" warning, because use_arch_info is only set after the
+ * first failure.
+ */
+ if (ret && use_arch_cache_info()) {
use_arch_info = true;
+ ret = 0;
+ }
return ret;
}
---
base-commit: a87737435cfa134f9cdcc696ba3080759d04cf72
change-id: 20260609-cacheinfo-b2a8d27a19ce
Best regards,
--
Breno Leitao <leitao@debian.org>
next reply other threads:[~2026-06-09 16:24 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-09 16:23 Breno Leitao [this message]
2026-06-11 10:30 ` Pierre Gondois
2026-06-11 11:05 ` Breno Leitao
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