Re: [PATCH v6 01/11] ASoC: dt-bindings: renesas,fsi: add support multiple clocks

[Krzysztof Kozlowski <krzk@kernel.org>]

On Tue, Jun 09, 2026 at 06:38:26PM +0700, phucduc.bui@gmail.com wrote:
> From: bui duc phuc <phucduc.bui@gmail.com>
> 
> The FSI on r8a7740 requires the SPU bus/bridge clock to be enabled before
> accessing its registers. Without this clock, any register access leads to
> a system hang as the FSI block sits behind the SPU bus.
> Update the binding to support multiple clocks to properly describe the
> hardware clock tree, including:
>   - SPU bus/bridge clock (spu) for register access.
>   - CPG DIV6 clocks (icka/b) as functional clock.
>   - FSI dividers (diva/b) for audio clock generation.
>   - External clock inputs (xcka/b) provided by the board.
> The hardware supports several valid clock configurations. For example,
> when both FSIA and FSIB operate as slaves, only the fck and spu clocks
> are required. When a port operates as a master, it can use either an
> internal clock source (ickx + divx) or an external clock source
> (ickx + xckx). Therefore, while fck and spu are mandatory on r8a7740,
> the remaining clocks (icka/b, diva/b and xcka/b) are optional and depend
> on the selected master/slave configuration and clock source.
> Both sh73a0 and r8a7740 define the SPU DIV6 clock control register at
> 0xe6150084. The binding therefore documents the clocks supported by the
> FSI driver for these variants.
> 
> Signed-off-by: bui duc phuc <phucduc.bui@gmail.com>
> ---
> 
> Changes in v6:
>  - DT binding updates (drop uniqueItems, commit message) based on 
>    Krzysztof's feedback.
> Changes in v4:
>  - Update dt-bindings based on feedback from Krzysztof, Rob, and Geert.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof