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On multi-IRQ platforms (S32G2, MCF5441X), the additional IRQ lines (boff, err, secondary-mb) remain active so their handlers can fire while registers are inconsistent. Disable all registered IRQ lines around the IMASK/CTRL writes. This also fixes the resume path, which calls this function. Signed-off-by: Ciprian Marian Costea Reviewed-and-tested-by: Haibo Chen Tested-by: Enric Balletbo i Serra --- drivers/net/can/flexcan/flexcan-core.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/net/can/flexcan/flexcan-core.c b/drivers/net/can/flexcan/flexcan-core.c index f73ff442d530..7dde2e623def 100644 --- a/drivers/net/can/flexcan/flexcan-core.c +++ b/drivers/net/can/flexcan/flexcan-core.c @@ -1519,14 +1519,28 @@ static void flexcan_chip_interrupts_enable(const struct net_device *dev) { const struct flexcan_priv *priv = netdev_priv(dev); struct flexcan_regs __iomem *regs = priv->regs; + u32 quirks = priv->devtype_data.quirks; u64 reg_imask; disable_irq(dev->irq); + if (quirks & FLEXCAN_QUIRK_NR_IRQ_3) { + disable_irq(priv->irq_boff); + disable_irq(priv->irq_err); + } + if (quirks & FLEXCAN_QUIRK_SECONDARY_MB_IRQ) + disable_irq(priv->irq_secondary_mb); + priv->write(priv->reg_ctrl_default, ®s->ctrl); reg_imask = priv->rx_mask | priv->tx_mask; priv->write(upper_32_bits(reg_imask), ®s->imask2); priv->write(lower_32_bits(reg_imask), ®s->imask1); enable_irq(dev->irq); + if (quirks & FLEXCAN_QUIRK_SECONDARY_MB_IRQ) + enable_irq(priv->irq_secondary_mb); + if (quirks & FLEXCAN_QUIRK_NR_IRQ_3) { + enable_irq(priv->irq_boff); + enable_irq(priv->irq_err); + } } static void flexcan_chip_interrupts_disable(const struct net_device *dev) -- 2.43.0