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The major difference is that glymur integrates two codec cores (vcodec0 and vcodec1), while SM8550 has only one. Add glymur specific platform data, reusing SM8550 definitions wherever applicable. Reviewed-by: Vikash Garodia Reviewed-by: Dmitry Baryshkov Signed-off-by: Vishnu Reddy --- drivers/media/platform/qcom/iris/Makefile | 1 + .../platform/qcom/iris/iris_platform_common.h | 5 + .../platform/qcom/iris/iris_platform_glymur.c | 106 +++++++++++++++++++++ .../platform/qcom/iris/iris_platform_glymur.h | 17 ++++ .../media/platform/qcom/iris/iris_platform_vpu3x.c | 35 +++++++ drivers/media/platform/qcom/iris/iris_probe.c | 4 + drivers/media/platform/qcom/iris/iris_vpu3x.c | 3 + 7 files changed, 171 insertions(+) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile index 6deadd531c8e..6c45d4ad13a8 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -12,6 +12,7 @@ qcom-iris-objs += iris_buffer.o \ iris_hfi_gen2_packet.o \ iris_hfi_gen2_response.o \ iris_hfi_queue.o \ + iris_platform_glymur.o \ iris_platform_vpu2.o \ iris_platform_vpu3x.o \ iris_power.o \ diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 99f59b64f853..e182030bd537 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -39,6 +39,10 @@ struct iris_inst; #define MAX_HEVC_VBR_LAYER_HP_SLIDING_WINDOW 5 #define MAX_HIER_CODING_LAYER_GEN1 6 +#define VIDEO_REGION_SECURE_FW_REGION_ID 0 +#define VIDEO_REGION_VM0_SECURE_NP_ID 1 +#define VIDEO_REGION_VM0_NONSECURE_NP_ID 5 + enum stage_type { STAGE_1 = 1, STAGE_2 = 2, @@ -53,6 +57,7 @@ enum pipe_type { extern const struct iris_firmware_data iris_hfi_gen1_data; extern const struct iris_firmware_data iris_hfi_gen2_data; +extern const struct iris_platform_data glymur_data; extern const struct iris_platform_data qcs8300_data; extern const struct iris_platform_data sc7280_data; extern const struct iris_platform_data sm8250_data; diff --git a/drivers/media/platform/qcom/iris/iris_platform_glymur.c b/drivers/media/platform/qcom/iris/iris_platform_glymur.c new file mode 100644 index 000000000000..c42ac99870ed --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_glymur.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +#include "iris_core.h" +#include "iris_platform_common.h" +#include "iris_platform_glymur.h" + +const struct iris_power_domain_data iris_glymur_ctrl_data = { + .pd_names = (const char *[]) { + "venus", + }, + .pd_cnt = 1, + .clk_names = (const char *[]) { + "core_iface", "core_freerun", "core", + }, + .clk_cnt = 3, +}; + +const struct iris_power_domain_data iris_glymur_vcodec_data[] = { + { + .pd_names = (const char *[]) { + "vcodec0", + }, + .pd_cnt = 1, + .clk_names = (const char *[]) { + "vcodec0_iface", "vcodec0_core_freerun", "vcodec0_core", + }, + .clk_cnt = 3, + }, + { + .pd_names = (const char *[]) { + "vcodec1", + }, + .pd_cnt = 1, + .clk_names = (const char *[]) { + "vcodec1_iface", "vcodec1_core_freerun", "vcodec1_core", + }, + .clk_cnt = 3, + }, +}; + +const char * const iris_glymur_clk_reset_table[] = { + "core_bus", + "vcodec0_bus", + "core", + "vcodec0_core", + "vcodec1_bus", + "vcodec1_core", +}; + +const char * const iris_glymur_opp_clk_table[] = { + "vcodec0_core", + "vcodec1_core", + "core", + NULL, +}; + +const struct tz_cp_config iris_glymur_tz_cp_config[] = { + { + .cp_start = VIDEO_REGION_SECURE_FW_REGION_ID, + .cp_size = 0, + .cp_nonpixel_start = 0, + .cp_nonpixel_size = 0x1000000, + }, + { + .cp_start = VIDEO_REGION_VM0_SECURE_NP_ID, + .cp_size = 0, + .cp_nonpixel_start = 0x1000000, + .cp_nonpixel_size = 0x24800000, + }, + { + .cp_start = VIDEO_REGION_VM0_NONSECURE_NP_ID, + .cp_size = 0, + .cp_nonpixel_start = 0x25800000, + .cp_nonpixel_size = 0xda600000, + }, +}; + +int iris_glymur_init_cb_devs(struct iris_core *core) +{ + u64 dma_mask = core->iris_platform_data->dma_mask; + const u32 fw_fid = IOMMU_FID_IRIS_FIRMWARE; + struct device *dev; + + dev = iris_vpu_bus_create_device(core->dev, "iris-firmware", dma_mask, &fw_fid); + if (IS_ERR(dev)) + return PTR_ERR(dev); + + if (device_iommu_mapped(dev)) + core->fw_dev = dev; + else + device_unregister(dev); + + return 0; +} + +void iris_glymur_deinit_cb_devs(struct iris_core *core) +{ + if (core->fw_dev) + device_unregister(core->fw_dev); +} diff --git a/drivers/media/platform/qcom/iris/iris_platform_glymur.h b/drivers/media/platform/qcom/iris/iris_platform_glymur.h new file mode 100644 index 000000000000..1dae5764cb8c --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_glymur.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __IRIS_PLATFORM_GLYMUR_H__ +#define __IRIS_PLATFORM_GLYMUR_H__ + +extern const struct iris_power_domain_data iris_glymur_ctrl_data; +extern const struct iris_power_domain_data iris_glymur_vcodec_data[2]; +extern const char * const iris_glymur_clk_reset_table[6]; +extern const char * const iris_glymur_opp_clk_table[4]; +extern const struct tz_cp_config iris_glymur_tz_cp_config[3]; +int iris_glymur_init_cb_devs(struct iris_core *core); +void iris_glymur_deinit_cb_devs(struct iris_core *core); + +#endif /* __IRIS_PLATFORM_GLYMUR_H__ */ diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c index 72dd23dbe02a..4049e134c3f0 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -12,6 +12,7 @@ #include "iris_vpu_buffer.h" #include "iris_vpu_common.h" +#include "iris_platform_glymur.h" #include "iris_platform_qcs8300.h" #include "iris_platform_sm8550.h" #include "iris_platform_sm8650.h" @@ -48,6 +49,12 @@ static const struct iris_firmware_desc iris_vpu35_p4_gen2_desc = { .fwname = "qcom/vpu/vpu35_p4.mbn", }; +static const struct iris_firmware_desc iris_vpu36_p4_s7_gen2_desc = { + .firmware_data = &iris_hfi_gen2_data, + .get_vpu_buffer_size = iris_vpu_buf_size, + .fwname = "qcom/vpu/vpu36_p4_s7.mbn", +}; + static const u32 iris_fmts_vpu3x_dec[] = { [IRIS_FMT_H264] = V4L2_PIX_FMT_H264, [IRIS_FMT_HEVC] = V4L2_PIX_FMT_HEVC, @@ -83,6 +90,34 @@ static const struct tz_cp_config tz_cp_config_vpu3[] = { }, }; +const struct iris_platform_data glymur_data = { + .firmware_desc = &iris_vpu36_p4_s7_gen2_desc, + .vpu_ops = &iris_vpu36_ops, + .icc_tbl = iris_icc_info_vpu3x, + .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), + .clk_rst_tbl = iris_glymur_clk_reset_table, + .clk_rst_tbl_size = ARRAY_SIZE(iris_glymur_clk_reset_table), + .bw_tbl_dec = iris_bw_table_dec_vpu3x, + .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), + .ctrl_data = &iris_glymur_ctrl_data, + .vcodec_data = iris_glymur_vcodec_data, + .opp_pd_tbl = iris_opp_pd_table_vpu3x, + .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), + .opp_clk_tbl = iris_glymur_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask = 0xffe00000 - 1, + .inst_iris_fmts = iris_fmts_vpu3x_dec, + .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), + .inst_caps = &platform_inst_cap_sm8550, + .tz_cp_config_data = iris_glymur_tz_cp_config, + .tz_cp_config_data_size = ARRAY_SIZE(iris_glymur_tz_cp_config), + .num_vpp_pipe = 4, + .max_session_count = 16, + .num_cores = 2, + .max_core_mbpf = NUM_MBS_8K * 2, + .max_core_mbps = ((8192 * 4320) / 256) * 60, +}; + /* * Shares most of SM8550 data except: * - inst_caps to platform_inst_cap_qcs8300 diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c index 1e362570bb15..3537cf283f14 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -468,6 +468,10 @@ static const struct dev_pm_ops iris_pm_ops = { }; static const struct of_device_id iris_dt_match[] = { + { + .compatible = "qcom,glymur-iris", + .data = &glymur_data, + }, { .compatible = "qcom,qcs8300-iris", .data = &qcs8300_data, diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c index dc491a5aecf5..87a0a2546284 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -8,6 +8,7 @@ #include #include "iris_instance.h" +#include "iris_platform_glymur.h" #include "iris_vpu_common.h" #include "iris_vpu_register_defines.h" @@ -415,6 +416,8 @@ const struct vpu_ops iris_vpu36_ops = { .program_bootup_registers = iris_vpu36_program_bootup_registers, .calc_freq = iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode = iris_vpu36_set_hwmode, + .init_cb_devs = iris_glymur_init_cb_devs, + .deinit_cb_devs = iris_glymur_deinit_cb_devs, .check_core_load = iris_vpu36_check_core_load, .get_required_freq = iris_vpu36_get_required_freq, }; -- 2.34.1