From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D48BC405840 for ; Wed, 10 Jun 2026 11:16:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781090199; cv=none; b=KKaRd+yEM2jarVtkLmDNf9xuTvO9fa+c9bGDHDCFt/4JEf9jhbepPqHIctwa8jesZ1EYRyDV5tz7NSNisBYin4PKz7vT4gkWVlAUvGaKbCi4UVjyQvTHoHlAacLJ5Z54qswqv7yAnLBMQfugk03QzWuj6UrG6E60bEf6ngC+Eg8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781090199; c=relaxed/simple; bh=xez8sZ9RBjardGyxwof/z6L+iBEeg8HWFEWtgvkHEJU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SmfMu5kYq+PB1LECB0uYb+78N4Mog9npETRvnSkDIiNGZn0hZHA7GvVwrLLxoT+i3NzWcnhCTq1vHIkQ2MHE/ccwHzMrOe/RIbYahggeUGU4MxykbFBAV3tXe6vW3KECW/BLjEyLZIyhIjwa91P4K30TJSohCyX1IwFsjMw0Pqc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=T/IFvYT5; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=gsp+gEqI; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="T/IFvYT5"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="gsp+gEqI" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65A7hnMv530865 for ; Wed, 10 Jun 2026 11:16:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= S8AvQbz0GUV2gYsPFulvrX90R4zhqqBfaHsXuKf+vhg=; b=T/IFvYT5yr4vYmNm 3LSihRgLzLXWcnDbTvb1WT146lRi7YCqmRNMbTEkrJhFNhjguvHrKPG/E0KibUVS jEzXZE/YeJlR83hE4fOt/oL/EbIMP8K/4Rlcen42onuM00iGqD1V5J85tPws23Mk qBPbnov31sKijbzwMEJfCdru4Fa1Z2liaNfV/r4LX9nL2oZZHH5adQePGrL2LUu0 RDfaornDv3th34jR0NAt/UCJsrwctxeqQ4JqQDF9t4DHxSP3Q+7BKcm5EPb2qbUe qB4bHNFfv2kOzVmqQsinDe/QVtjMQ5wc+I0RQAUKfK9CPxy6aEpzfZjhhpl1jwKK DRK4KQ== Received: from mail-pg1-f199.google.com (mail-pg1-f199.google.com [209.85.215.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4epwnh27fp-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 10 Jun 2026 11:16:31 +0000 (GMT) Received: by mail-pg1-f199.google.com with SMTP id 41be03b00d2f7-c85a2cde332so3314581a12.3 for ; Wed, 10 Jun 2026 04:16:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1781090191; x=1781694991; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=S8AvQbz0GUV2gYsPFulvrX90R4zhqqBfaHsXuKf+vhg=; b=gsp+gEqIJQM8iBV8Wu544A1RYe7C8UVnwWP2UxEMyZ6nKUM4J4M85rPnuUOT7gam2B GnDVirEFNPpAxmSPuZrfGlYZazls7qjPU/QCRKyLJRUVcvXtG2BrWssmDbzVxu1NB5Gb RnVU6JShVdIt1rOLCYvx8YnUHok80rgOi+PCQ+Mzzn3QS77GIvLu/oBltmnTGiLI3YKC hBvwnknzJ6qHxEuej7D8ZzKjWcP+6wkaCY+br9iGeGOwRzyQFjEWokGu3Ruh1hSad0e9 RO1Nugwc0eWp8tGJ6c6uIs4m6fmnHOXBSZ+8FxPx1ZvqUenZlnB+swPzzHAQw1cQHLJB jo8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781090191; x=1781694991; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=S8AvQbz0GUV2gYsPFulvrX90R4zhqqBfaHsXuKf+vhg=; b=T8saUbsCT4VfyhnfR3pUxXZ0HKYIfqLvBetS6KGEewsEFWPDFZGtGrcE1MRJQUiuGb STpQWDAUivd4NN6zHQMRdwQOigAtVk6kiGmKTGZh/C6n7mtzgAlRmRxRiRioMPWzqkQP Po//XafmvdbgWXW/Ct1sr7akT6FYFvWpC2+ETqyYn+hKlY1dezT/BgNhjrKqw5SibIFN CTNPYaYQjtbMNVD0rFMvKMB2zIti3pekF0AH/d3uB0MSfCeRnxd0RvQlI6Q8aMDsxCBl VE0iI0UU6Y91DM8FjywBRZysJVe1kIbXNxd6gWyzuVRHjCN1JAibnh1cnomOJ1R4vAxL DGug== X-Forwarded-Encrypted: i=1; AFNElJ9UTNz5GgV0NTbQUrxPOyR1muEQzjHLUNz6ofZBTHnarjB4t37xF4nzeIGD92g0uMyjl24EsFqViMnEpEE=@vger.kernel.org X-Gm-Message-State: AOJu0YyVEBCfRSBD0XrQe5t9BqajVCvkmtCfZ4VMVeFVD5WOxDyv4/ud TWXT02tryc4HiBdvVnYgpdwJYjbbxmZQIqVQD7lkd3+A0+Bz+ZDg/hjRLhgCs4pgzVijhIteQY9 jAkMwqpBC6ayMCAOVSpHzsWBB9wlWA0uYQPLY7sdS068TXgwFlwbEdsBa1w6FevIpAG0= X-Gm-Gg: Acq92OFcidHMBS0PFsugv/Dp9D04uOhsNQRVpa7TlDqfyU5GxGWoZLgfFHzs9Urafkz hp/pkkYYt/v/kB57p++hGPCQEIcXp0Vf65wQ18enYzOFGyzTNdkyobgSGrzipqoYPvaStxsOb0K EGsE6GmehHALEdxQIEvsi7BcYll21hacqYDdrwXQRATDwCl2UOK/9AzU0DuwyPWdu+Q5k0EOPj6 mrNkrL/Ea4Ibsy2+aEvyfYmkZvz5kBGYBNrzVgcFv/oq3oo7WBw5EvRd1qwyHVGSf1MXxFiRh5Q pxaXOBkbiPqp/mogxMetJkBi89T5G4v2sTJuG3cRuyWclVo595LBoI6c6PNMK+oP17b5T8QTe5N qR347CENyrBJjce4icQOLr3uvJnY2Xo6zXY+ZcIrxMJGXTU+c8C3BVLTstj0TtKNfMNf96vigfi PdzG/hQLyqoOIZqEXC3qION/3M65KkDYhjdG6we6bgycBWgNGH1AeAF0qPL9Gxrg== X-Received: by 2002:a05:6a20:3d0e:b0:39b:87f0:758e with SMTP id adf61e73a8af0-3b4cccfdd99mr31753453637.8.1781090191179; Wed, 10 Jun 2026 04:16:31 -0700 (PDT) X-Received: by 2002:a05:6a20:3d0e:b0:39b:87f0:758e with SMTP id adf61e73a8af0-3b4cccfdd99mr31753403637.8.1781090190624; Wed, 10 Jun 2026 04:16:30 -0700 (PDT) Received: from hu-varada-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c85df03498csm23896099a12.1.2026.06.10.04.16.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2026 04:16:30 -0700 (PDT) From: Varadarajan Narayanan Date: Wed, 10 Jun 2026 16:46:09 +0530 Subject: [PATCH v3 2/2] phy: qcom-qmp-pcie: Add support for ipq5210 PCIe phys Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260610-pcie-phy-v3-2-334011b378d6@oss.qualcomm.com> References: <20260610-pcie-phy-v3-0-334011b378d6@oss.qualcomm.com> In-Reply-To: <20260610-pcie-phy-v3-0-334011b378d6@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjEwMDEwNyBTYWx0ZWRfXwQ3pXzxsa4aO DGBTDygRS+3nsjGltthFJymif/zn/q1g47iJIuDhtB/MiwJhnpbze6gBmf/eNJgQN6V5hHe9ZQM RhKsFHnGNP6OBc/ECtsx9fiGGPfRFgEkL1NCM+PnZudzcAgL2tPJp79z/966rl44ceprguXZHXe 2uKnGxqkPsMnGQ0Vqyn0tCv3CLemcBQ3AzmrMftE3EhQkDIizzCm/7yRuXwx4lluID2xV0pYG2M 5YuIfxNIbPwifMrbHC4ljdeIQRrks/PBlnTMaHFediUrd/pIAOR9krllwvaTBa7FW3t3iOjD39U 1xQtkokqZhs+Wj3T7SCClwHSiVRmYASPYNQiz3MVJiKsDqJQwRs+EzLFYR7IXDCzVqfp3SZ5Lj7 kfgEta1c7bFaUaC6Bys89OuQu9VfM8Jfuml+d+yZXtEJe5oYgIdHIbhZm1C325fgVC6Ku+o1rks z25PeuhEeDiBajaQ5dQ== X-Authority-Analysis: v=2.4 cv=Xce5Co55 c=1 sm=1 tr=0 ts=6a29478f cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=lQuujfteSIboIXYB3dUA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-ORIG-GUID: Nrh0IpsmBaRQhaLUj5oD7Q4tyxdk2KHz X-Proofpoint-GUID: Nrh0IpsmBaRQhaLUj5oD7Q4tyxdk2KHz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-10_02,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 malwarescore=0 impostorscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 bulkscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606100107 Add support for a PCIe phys found on Qualcomm ipq5210 platform. Signed-off-by: Varadarajan Narayanan --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 129 +++++++++++++++++++++++++++++++ 1 file changed, 129 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 75afbd15aaf4..2bf00e0e125a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -514,6 +514,89 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), }; +static const struct qmp_phy_init_tbl ipq5210_gen3x1_pcie_ep_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x02), + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xff), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x09), + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x23), + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x23), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x10), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x10), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x19), + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xfe), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xfe), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x07), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x10), +}; + +static const struct qmp_phy_init_tbl ipq5210_gen3x1_pcie_ep_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), +}; + +static const struct qmp_phy_init_tbl ipq5210_gen3x1_pcie_ep_pcs_misc_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x04), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG1, 0x02), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG4, 0xff), +}; + static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), @@ -3613,6 +3696,49 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { .phy_status = PHYSTATUS, }; +static const struct qmp_phy_cfg ipq5210_gen3x1_pciephy_cfg = { + .lanes = 1, + + .offsets = &qmp_pcie_offsets_v4x1, + + .tbls = { + .serdes = ipq9574_gen3x1_pcie_serdes_tbl, + .serdes_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_serdes_tbl), + .tx = ipq8074_pcie_gen3_tx_tbl, + .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), + .rx = ipq9574_pcie_rx_tbl, + .rx_num = ARRAY_SIZE(ipq9574_pcie_rx_tbl), + .pcs = ipq9574_gen3x1_pcie_pcs_tbl, + .pcs_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_tbl), + .pcs_misc = ipq9574_gen3x1_pcie_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_misc_tbl), + }, + + .tbls_ep = &(const struct qmp_phy_cfg_tbls) { + .serdes = ipq5210_gen3x1_pcie_ep_serdes_tbl, + .serdes_num = ARRAY_SIZE(ipq5210_gen3x1_pcie_ep_serdes_tbl), + .tx = ipq6018_pcie_tx_tbl, + .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl), + .rx = ipq5210_gen3x1_pcie_ep_rx_tbl, + .rx_num = ARRAY_SIZE(ipq5210_gen3x1_pcie_ep_rx_tbl), + .pcs = ipq6018_pcie_pcs_tbl, + .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl), + .pcs_misc = ipq5210_gen3x1_pcie_ep_pcs_misc_tbl, + .pcs_misc_num = ARRAY_SIZE(ipq5210_gen3x1_pcie_ep_pcs_misc_tbl), + }, + + .reset_list = ipq8074_pciephy_reset_l, + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), + .vreg_list = NULL, + .num_vregs = 0, + .regs = pciephy_v4_regs_layout, + + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS, + + .pipe_clock_rate = 250000000, +}; + static const struct qmp_phy_cfg ipq9574_gen3x1_pciephy_cfg = { .lanes = 1, @@ -5404,6 +5530,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { }, { .compatible = "qcom,glymur-qmp-gen5x4-pcie-phy", .data = &glymur_qmp_gen5x4_pciephy_cfg, + }, { + .compatible = "qcom,ipq5210-qmp-gen3x1-pcie-phy", + .data = &ipq5210_gen3x1_pciephy_cfg, }, { .compatible = "qcom,ipq6018-qmp-pcie-phy", .data = &ipq6018_pciephy_cfg, -- 2.34.1