From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9A1139E6CD; Wed, 10 Jun 2026 08:09:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781078963; cv=none; b=UnlPZPXHeNCusfrNba1PN0reVLqD/AhTOhRn3PN9Bku6OTv7KUfnur/QXrPdXYQ9LE0RdHUMza8i2FnCH7GcvmMVigiydnf8Jps0XzBDCGi281E9TmyEc9ILVW7w0rAkQbycf7FUbH50Px0Y+ojM4obOkpy6+C/27vANG3fJEZk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781078963; c=relaxed/simple; bh=E5P2Gjp4/BbQBOwFdi1OgqPZmBHnmNDC1bxdVPboHIg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Nbd/RHUXDD3otCnlJlsCvcdEETy1KBZzGBcRLBXcyXGDuwVImcQPWvlNFB+qAOeNgJb6mjoMFuTL8Kkd1qwLzZb+fKKzC2kBz9dPA+RQADCvmjKJCXISDowcu5g1kT7PJSQLi0foZR/BozDmfbYDgTqC5TRCnLpycY/zXPB3lyQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=DcKKbmkc; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="DcKKbmkc" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 65A88QhK4983537, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1781078906; bh=YM/WzGB54qg+7zNwVx31dRrfeQidylWsP1EVolYAyUU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=DcKKbmkc68/g1XDFZ8gkR1WeIbnUoOG7wyPaABRHd1tsbtLAnpboI2FdnOw0kBfea MuA5b9PaQmtKipfAMy6gCPf6oHOoXzeDm3gQfVQ+t1Em3ESCQNmyXJAWkYpN+iH2Yk ojE2aC3z+6DCMCa3YOr7ib5hmKr6LYWJOY/G6A2PRp8ZUfEBL03+gO8no2ogs/ORdl iHIF1qvjkW+aeCRdezFaGYf/kI3BB1HOWPZDSdpJoh+yT/q5M/rtEcCa6y8pTYG5ix nNy15CeEj/8w/06wqsOgl9uFAG5+k7a/ajK1yrJ3/pcIGNKq7Otby/ta50w+F+pkju E1GYou61/whfg== Received: from mail.realtek.com (rtkexhmbs02.realtek.com.tw[172.21.6.41]) by rtits2.realtek.com.tw (8.15.2/3.29/5.94) with ESMTPS id 65A88QhK4983537 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 10 Jun 2026 16:08:26 +0800 Received: from RTKEXHMBS03.realtek.com.tw (10.21.1.53) by RTKEXHMBS02.realtek.com.tw (172.21.6.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Wed, 10 Jun 2026 16:08:25 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS03.realtek.com.tw (10.21.1.53) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Wed, 10 Jun 2026 16:08:25 +0800 From: Yu-Chun Lin To: , , , , , , , , CC: , , , , , , , , , Subject: [PATCH v8 02/10] reset: Add Realtek basic reset support Date: Wed, 10 Jun 2026 16:08:16 +0800 Message-ID: <20260610080824.255063-3-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260610080824.255063-1-eleanor.lin@realtek.com> References: <20260610080824.255063-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain From: Cheng-Yu Lee Define the reset operations backed by a regmap-based register interface and prepare the reset controller to be registered through the reset framework. Since the reset controllers on Realtek SoCs often share the same register space with the clock controllers, this common framework is designed to extract the regmap and device tree node from the parent device (e.g., an auxiliary device parent). Signed-off-by: Cheng-Yu Lee Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin --- Changes in v8: - None --- MAINTAINERS | 1 + drivers/reset/Kconfig | 1 + drivers/reset/Makefile | 1 + drivers/reset/realtek/Kconfig | 8 +++ drivers/reset/realtek/Makefile | 2 + drivers/reset/realtek/common.c | 90 ++++++++++++++++++++++++++++++++++ drivers/reset/realtek/common.h | 29 +++++++++++ 7 files changed, 132 insertions(+) create mode 100644 drivers/reset/realtek/Kconfig create mode 100644 drivers/reset/realtek/Makefile create mode 100644 drivers/reset/realtek/common.c create mode 100644 drivers/reset/realtek/common.h diff --git a/MAINTAINERS b/MAINTAINERS index 613ca7e95e47..80e840a6691d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22484,6 +22484,7 @@ L: devicetree@vger.kernel.org L: linux-clk@vger.kernel.org S: Supported F: Documentation/devicetree/bindings/clock/realtek* +F: drivers/reset/realtek/* F: include/dt-bindings/clock/realtek* F: include/dt-bindings/reset/realtek* diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index d009eb0849a3..45a4227b5f44 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -418,6 +418,7 @@ config RESET_ZYNQMP source "drivers/reset/amlogic/Kconfig" source "drivers/reset/hisilicon/Kconfig" +source "drivers/reset/realtek/Kconfig" source "drivers/reset/spacemit/Kconfig" source "drivers/reset/starfive/Kconfig" source "drivers/reset/sti/Kconfig" diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 3e52569bd276..7330fee91365 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -2,6 +2,7 @@ obj-y += core.o obj-y += amlogic/ obj-y += hisilicon/ +obj-y += realtek/ obj-y += spacemit/ obj-y += starfive/ obj-y += sti/ diff --git a/drivers/reset/realtek/Kconfig b/drivers/reset/realtek/Kconfig new file mode 100644 index 000000000000..bb6dd856a64a --- /dev/null +++ b/drivers/reset/realtek/Kconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only +config RESET_RTK_COMMON + tristate "Realtek common reset driver" if COMPILE_TEST + help + This option enables the common reset controller library for + Realtek SoCs. It provides shared reset control operations + (assert, deassert, status) and a registration helper function + that other Realtek-specific reset drivers can use. diff --git a/drivers/reset/realtek/Makefile b/drivers/reset/realtek/Makefile new file mode 100644 index 000000000000..b59a3f7f2453 --- /dev/null +++ b/drivers/reset/realtek/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_RESET_RTK_COMMON) += common.o diff --git a/drivers/reset/realtek/common.c b/drivers/reset/realtek/common.c new file mode 100644 index 000000000000..2ce20c25377b --- /dev/null +++ b/drivers/reset/realtek/common.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2019-2026 Realtek Semiconductor Corporation + */ + +#include +#include +#include +#include +#include +#include "common.h" + +static inline struct rtk_reset_data *to_rtk_reset_controller(struct reset_controller_dev *r) +{ + return container_of(r, struct rtk_reset_data, rcdev); +} + +static inline const struct rtk_reset_desc *rtk_reset_get_desc(struct rtk_reset_data *data, + unsigned long idx) +{ + return &data->descs[idx]; +} + +static int rtk_reset_assert(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + struct rtk_reset_data *data = to_rtk_reset_controller(rcdev); + const struct rtk_reset_desc *desc; + u32 mask, val; + + desc = rtk_reset_get_desc(data, idx); + mask = desc->write_en ? (0x3U << desc->bit) : BIT(desc->bit); + val = desc->write_en ? (0x2U << desc->bit) : 0; + + return regmap_update_bits(data->regmap, desc->ofs, mask, val); +} + +static int rtk_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + struct rtk_reset_data *data = to_rtk_reset_controller(rcdev); + const struct rtk_reset_desc *desc; + u32 mask, val; + + desc = rtk_reset_get_desc(data, idx); + mask = desc->write_en ? (0x3U << desc->bit) : BIT(desc->bit); + val = mask; + + return regmap_update_bits(data->regmap, desc->ofs, mask, val); +} + +static int rtk_reset_status(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + struct rtk_reset_data *data = to_rtk_reset_controller(rcdev); + const struct rtk_reset_desc *desc; + u32 val; + int ret; + + desc = rtk_reset_get_desc(data, idx); + ret = regmap_read(data->regmap, desc->ofs, &val); + if (ret) + return ret; + + return !((val >> desc->bit) & 1); +} + +static const struct reset_control_ops rtk_reset_ops = { + .assert = rtk_reset_assert, + .deassert = rtk_reset_deassert, + .status = rtk_reset_status, +}; + +/* The caller must initialize data->descs, data->rcdev.nr_resets and + * data->rcdev.owner before calling rtk_reset_controller_add(). + */ +int rtk_reset_controller_add(struct device *dev, + struct rtk_reset_data *data) +{ + data->regmap = dev_get_platdata(dev); + data->rcdev.ops = &rtk_reset_ops; + data->rcdev.dev = dev; + data->rcdev.of_node = dev->parent->of_node; + + return devm_reset_controller_register(dev, &data->rcdev); +} +EXPORT_SYMBOL_NS_GPL(rtk_reset_controller_add, "REALTEK_RESET"); + +MODULE_DESCRIPTION("realtek reset infrastructure"); +MODULE_LICENSE("GPL"); diff --git a/drivers/reset/realtek/common.h b/drivers/reset/realtek/common.h new file mode 100644 index 000000000000..42eb41eae2ec --- /dev/null +++ b/drivers/reset/realtek/common.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 Realtek Semiconductor Corporation + * Author: Yu-Chun Lin + */ + +#ifndef __RESET_REALTEK_COMMON_H +#define __RESET_REALTEK_COMMON_H + +#include + +struct regmap; + +struct rtk_reset_desc { + u32 ofs; + u32 bit; + bool write_en; +}; + +struct rtk_reset_data { + struct reset_controller_dev rcdev; + const struct rtk_reset_desc *descs; + struct regmap *regmap; +}; + +int rtk_reset_controller_add(struct device *dev, + struct rtk_reset_data *initdata); + +#endif /* __RESET_REALTEK_COMMON_H */ -- 2.43.0