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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c24edbb49bsm140980535ad.38.2026.06.11.02.03.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jun 2026 02:03:33 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Thu, 11 Jun 2026 14:33:18 +0530 Subject: [PATCH v2 3/3] regulator: qcom-refgen: add support for the IPQ9650 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260611-ipq9650_refgen-v2-3-d96a91d5b99e@oss.qualcomm.com> References: <20260611-ipq9650_refgen-v2-0-d96a91d5b99e@oss.qualcomm.com> In-Reply-To: <20260611-ipq9650_refgen-v2-0-d96a91d5b99e@oss.qualcomm.com> To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Kathiravan Thirumoorthy X-Mailer: b4 0.15.2 X-Authority-Analysis: v=2.4 cv=GbMnWwXL c=1 sm=1 tr=0 ts=6a2a79e7 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=Z5Z_lLKGqtEyjnyCENkA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-ORIG-GUID: 1avBB86L3mIrPsha44E1wP1MIBbW0BLJ X-Proofpoint-GUID: 1avBB86L3mIrPsha44E1wP1MIBbW0BLJ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjExMDA4OSBTYWx0ZWRfXwYX58tvjRqNG lECS9Ff1HetZkrokF3Yt8cYpbgELhqyn6vviBLABQTq10yc1shR3bUwaf7Xd4N9Jo3sRwdnTZDg 08F6/ySKIiGo/1OrPBlTAI2pnOdyDDeiZqkxQX0u34vMt+LOWkp3rHfN7dBCS6M6NYavJVlD4OA ntm+vMzrsz4FYaBxT+apqrwA4ltin9uilOXnf3UOWx7Wnm+39u48nPiWgA/IpYxJ5lmQ72IpXUV ZXlIUF8pMQpvHUL7K8hbnB8OsV7AcRBFoK7v40u4cdesKgjlUeD6Lq6bIXSn3c3uw81BtWZ0/G8 hc4dHpEng4ObNIsaqbke+PbnwT6+K5UZQW6ulB8zHtYlQVYnScDyKlZMqKV/h3SrLibyz8BCMZn tldNLeD5lI/D53JFk5nnWIUijJ5VORayhQ1T2JvAq8WXTV8GXLST6Iwo977eNI1cw4TQ3FtEiLj UBWQj9af6yxjHI2PsgQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwNjExMDA4OSBTYWx0ZWRfXxM8QNYlbOnO0 Bybso057ARP9tsW/seRUD17yJEHIlIifWjHV7BeOYENfZ3F4ebjWQ/8xGa3M3d7VepmzNP+fL/1 44tWG+94rB23GHANJL0zirZaDVUsB1M= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-11_01,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 bulkscore=0 adultscore=0 spamscore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606110089 IPQ9650 SoC has 2 REFGEN blocks providing the reference current to the PCIe and USB, UNIPHY PHYs. For the other SoCs, clocks for this block is enabled on power up but that's not the case for IPQ9650 and we have to enable those clocks explicitly to bring up the PHYs properly. Signed-off-by: Kathiravan Thirumoorthy --- drivers/regulator/qcom-refgen-regulator.c | 89 +++++++++++++++++++++++++++++-- 1 file changed, 85 insertions(+), 4 deletions(-) diff --git a/drivers/regulator/qcom-refgen-regulator.c b/drivers/regulator/qcom-refgen-regulator.c index 6a3795469927..e8821f159ff1 100644 --- a/drivers/regulator/qcom-refgen-regulator.c +++ b/drivers/regulator/qcom-refgen-regulator.c @@ -3,6 +3,7 @@ // Copyright (c) 2023, Linaro Limited #include +#include #include #include #include @@ -16,6 +17,10 @@ #define REFGEN_BIAS_EN_ENABLE 0x7 #define REFGEN_BIAS_EN_DISABLE 0x6 +#define REFGEN_REG_REFGEN_STATUS 0xC +#define REFGEN_STATUS_OUT_MASK BIT(3) + #define REFGEN_STATUS_OUT_ENABLE 0x8 + #define REFGEN_REG_BG_CTRL 0x14 #define REFGEN_BG_CTRL_MASK GENMASK(2, 1) #define REFGEN_BG_CTRL_ENABLE 0x3 @@ -25,6 +30,16 @@ #define REFGEN_PWRDWN_CTRL5_MASK BIT(0) #define REFGEN_PWRDWN_CTRL5_ENABLE 0x1 +struct qcom_refgen_regulator_data { + const struct regulator_desc *rdesc; + bool has_clocks; +}; + +struct qcom_refgen_drvdata { + struct clk_bulk_data *clks; + int num_clks; +}; + static int qcom_sdm845_refgen_enable(struct regulator_dev *rdev) { regmap_update_bits(rdev->regmap, REFGEN_REG_BG_CTRL, REFGEN_BG_CTRL_MASK, @@ -62,6 +77,42 @@ static int qcom_sdm845_refgen_is_enabled(struct regulator_dev *rdev) return 1; } +static int qcom_ipq9650_refgen_enable(struct regulator_dev *rdev) +{ + struct qcom_refgen_drvdata *drvdata = rdev_get_drvdata(rdev); + int ret; + + ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clks); + if (ret) + return ret; + + return 0; +} + +static int qcom_ipq9650_refgen_disable(struct regulator_dev *rdev) +{ + struct qcom_refgen_drvdata *drvdata = rdev_get_drvdata(rdev); + + clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clks); + + return 0; +} + +static const struct regulator_desc ipq9650_refgen_desc = { + .enable_reg = REFGEN_REG_REFGEN_STATUS, + .enable_mask = REFGEN_STATUS_OUT_MASK, + .enable_val = REFGEN_STATUS_OUT_ENABLE, + .enable_time = 5, + .name = "refgen", + .owner = THIS_MODULE, + .type = REGULATOR_CURRENT, + .ops = &(const struct regulator_ops) { + .enable = qcom_ipq9650_refgen_enable, + .disable = qcom_ipq9650_refgen_disable, + .is_enabled = regulator_is_enabled_regmap, + }, +}; + static const struct regulator_desc sdm845_refgen_desc = { .enable_time = 5, .name = "refgen", @@ -90,6 +141,19 @@ static const struct regulator_desc sm8250_refgen_desc = { }, }; +static const struct qcom_refgen_regulator_data ipq9650_data = { + .rdesc = &ipq9650_refgen_desc, + .has_clocks = true, +}; + +static const struct qcom_refgen_regulator_data sdm845_data = { + .rdesc = &sdm845_refgen_desc, +}; + +static const struct qcom_refgen_regulator_data sm8250_data = { + .rdesc = &sm8250_refgen_desc, +}; + static const struct regmap_config qcom_refgen_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -98,6 +162,8 @@ static const struct regmap_config qcom_refgen_regmap_config = { static int qcom_refgen_probe(struct platform_device *pdev) { + const struct qcom_refgen_regulator_data *data; + struct qcom_refgen_drvdata *drvdata = NULL; struct regulator_init_data *init_data; struct regulator_config config = {}; const struct regulator_desc *rdesc; @@ -106,10 +172,23 @@ static int qcom_refgen_probe(struct platform_device *pdev) struct regmap *regmap; void __iomem *base; - rdesc = of_device_get_match_data(dev); - if (!rdesc) + data = of_device_get_match_data(dev); + if (!data) return -ENODATA; + if (data->has_clocks) { + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->num_clks = devm_clk_bulk_get_all(dev, &drvdata->clks); + if (drvdata->num_clks < 0) + return dev_err_probe(dev, drvdata->num_clks, + "failed to get clocks\n"); + } + + rdesc = data->rdesc; + base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); @@ -126,6 +205,7 @@ static int qcom_refgen_probe(struct platform_device *pdev) config.init_data = init_data; config.of_node = dev->of_node; config.regmap = regmap; + config.driver_data = drvdata; rdev = devm_regulator_register(dev, rdesc, &config); if (IS_ERR(rdev)) @@ -135,8 +215,9 @@ static int qcom_refgen_probe(struct platform_device *pdev) } static const struct of_device_id qcom_refgen_match_table[] = { - { .compatible = "qcom,sdm845-refgen-regulator", .data = &sdm845_refgen_desc }, - { .compatible = "qcom,sm8250-refgen-regulator", .data = &sm8250_refgen_desc }, + { .compatible = "qcom,ipq9650-refgen-regulator", .data = &ipq9650_data }, + { .compatible = "qcom,sdm845-refgen-regulator", .data = &sdm845_data }, + { .compatible = "qcom,sm8250-refgen-regulator", .data = &sm8250_data }, { } }; MODULE_DEVICE_TABLE(of, qcom_refgen_match_table); -- 2.34.1