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Wed, 10 Jun 2026 22:00:10 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c164f8bc5asm276188335ad.27.2026.06.10.22.00.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2026 22:00:10 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:55 +0530 Subject: [PATCH v2 19/37] arm64: dts: qcom: lemans: Move PCIe phy and GPIOs to root port node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260611-wake-v2-19-2744251b1181@oss.qualcomm.com> References: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com> In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , cros-qcom-dts-watchers@chromium.org, Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krishna Chaitanya Chundru , Krishna Chaitanya Chundru X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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Move phys from the controller to pcieport0 and pcieport1. Add the missing pcieport1 label to the pcie1 root port node to allow board-level overrides. Move perst-gpios/wake-gpios from the &pcie0/&pcie1 controller overrides to the respective &pcieport0/ &pcieport1 nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 16 ++++++++++------ arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi | 16 ++++++++++------ arch/arm64/boot/dts/qcom/lemans.dtsi | 12 +++++------- 3 files changed, 25 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index fe9a2cd325d4..f492a294ee5b 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -702,15 +702,17 @@ &mdss0_dp1_phy { }; &pcie0 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcieport0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l1c>; @@ -719,15 +721,17 @@ &pcie0_phy { }; &pcie1 { - perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcieport1 { + reset-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l1c>; diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index 3a6d73b485a9..d6c5a8b49fa5 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -853,25 +853,29 @@ wake-pins { }; &pcie0 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; status = "okay"; }; -&pcie1 { - perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; +&pcieport0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; +}; +&pcie1 { pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; status = "okay"; }; +&pcieport1 { + reset-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l1c>; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index fe6e76351823..48d50a0dc05f 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -8678,9 +8678,6 @@ pcie0: pcie@1c00000 { power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; eq-presets-16gts = /bits/ 8 <0x55 0x55>; @@ -8691,6 +8688,8 @@ pcieport0: pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie0_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -8851,19 +8850,18 @@ pcie1: pcie@1c10000 { power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; status = "disabled"; - pcie@0 { + pcieport1: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie1_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; -- 2.34.1