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Wed, 10 Jun 2026 22:00:26 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c164f8bc5asm276188335ad.27.2026.06.10.22.00.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2026 22:00:25 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:59 +0530 Subject: [PATCH v2 23/37] arm64: dts: qcom: sa8295p: Move PCIe GPIOs to root port node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260611-wake-v2-23-2744251b1181@oss.qualcomm.com> References: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com> In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , cros-qcom-dts-watchers@chromium.org, Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krishna Chaitanya Chundru , Krishna Chaitanya Chundru X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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Move perst-gpios/ wake-gpios from the &pcie2a, &pcie3a, &pcie3b, and &pcie4 controller overrides to the respective &pcie2a_port0, &pcie3a_port0, &pcie3b_port0, and &pcie4_port0 nodes, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index d28d69162427..512de3597581 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -453,15 +453,17 @@ &mdss1_dp3_phy { }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie2a_default>; status = "okay"; }; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie2a_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; @@ -472,15 +474,17 @@ &pcie2a_phy { &pcie3a { num-lanes = <2>; - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie3a_default>; status = "okay"; }; +&pcie3a_port0 { + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; +}; + &pcie3a_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; @@ -489,15 +493,17 @@ &pcie3a_phy { }; &pcie3b { - perst-gpios = <&tlmm 153 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie3b_default>; status = "okay"; }; +&pcie3b_port0 { + reset-gpios = <&tlmm 153 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>; +}; + &pcie3b_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; @@ -506,15 +512,17 @@ &pcie3b_phy { }; &pcie4 { - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie4_default>; status = "okay"; }; +&pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; +}; + &pcie4_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; -- 2.34.1