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Move phys and phy-names from the controller to pcie0_port0, pcie1_port0, pcie2_port0, and pcie3_port0, adding labels to these nodes to allow board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru --- .../arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 7 +++++-- arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 7 +++++-- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 24 +++++++++++----------- 3 files changed, 22 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 44bf3db01d3a..c2d9dcf8ed64 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -457,14 +457,17 @@ &mdss_edp_out { }; &pcie3 { - perst-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 180 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie3_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcie3_port0 { + reset-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 180 GPIO_ACTIVE_LOW>; +}; + &pcie3_phy { vdda-phy-supply = <&vreg_l5e_0p88>; vdda-pll-supply = <&vreg_l3c_1p2>; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index a4644ecca536..1b50baf0271b 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -558,14 +558,17 @@ &mdss_edp_out { }; &pcie1 { - perst-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 177 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie2_default_state>; status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 177 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l5e_0p88>; vdda-pll-supply = <&vreg_l3c_1p2>; diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index f45deb188c6c..b6966ec7790f 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -1779,13 +1779,11 @@ pcie0: pcie@1c00000 { <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - phys = <&pcie0_phy>; - phy-names = "pciephy"; dma-coherent; status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -1793,6 +1791,8 @@ pcie@0 { #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie0_phy>; }; }; @@ -1898,13 +1898,11 @@ pcie3: pcie@1c08000 { <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_3 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - phys = <&pcie3_phy>; - phy-names = "pciephy"; dma-coherent; status = "disabled"; - pcie@0 { + pcie3_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -1912,6 +1910,8 @@ pcie@0 { #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie3_phy>; }; }; @@ -2018,13 +2018,11 @@ pcie1: pcie@1c10000 { <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_1 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - phys = <&pcie1_phy>; - phy-names = "pciephy"; dma-coherent; status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2032,6 +2030,8 @@ pcie@0 { #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie1_phy>; }; }; @@ -2138,13 +2138,11 @@ pcie2: pcie@1c18000 { <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_2 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - phys = <&pcie2_phy>; - phy-names = "pciephy"; dma-coherent; status = "disabled"; - pcie@0 { + pcie2_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2152,6 +2150,8 @@ pcie@0 { #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie2_phy>; }; }; -- 2.34.1