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Wed, 10 Jun 2026 22:00:57 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c164f8bc5asm276188335ad.27.2026.06.10.22.00.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2026 22:00:56 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:07 +0530 Subject: [PATCH v2 31/37] arm64: dts: qcom: sm8350: Move PCIe phy and GPIOs to root port node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260611-wake-v2-31-2744251b1181@oss.qualcomm.com> References: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com> In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , cros-qcom-dts-watchers@chromium.org, Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krishna Chaitanya Chundru , Krishna Chaitanya Chundru X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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Move phys and phy-names from the controller to pcie0_port0 and pcie1_port0, adding labels to these nodes to allow board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board file, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 16 ++++++++++------ arch/arm64/boot/dts/qcom/sm8350.dtsi | 14 ++++++-------- 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 0897ed1bbc6f..9a14973fd972 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -493,12 +493,14 @@ &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - status = "okay"; }; +&pcie0_port0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l5b_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; @@ -507,15 +509,17 @@ &pcie0_phy { }; &pcie1 { - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { status = "okay"; vdda-phy-supply = <&vreg_l5b_0p88>; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index c830953156ec..4515a1ccb930 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1583,12 +1583,9 @@ pcie0: pcie@1c00000 { power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -1596,6 +1593,8 @@ pcie@0 { #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie0_phy>; }; }; @@ -1692,12 +1691,9 @@ pcie1: pcie@1c08000 { power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -1705,6 +1701,8 @@ pcie@0 { #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie1_phy>; }; }; -- 2.34.1