From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2E43395AF0 for ; Thu, 11 Jun 2026 05:01:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781154085; cv=none; b=qOEA6PLgTf4WLHpbKlTy2vhjeKXGkeElouyDBhKkDNCdulP7YFtpdurl72wLkXM6jqT1niVt3kdWMyKXtLixGSu9/dN40pYZEdWWsKy2QxxiIy/x0gknha3i+C92xIkqLWYduZEqGYtwC3UeRvNaemR8AIs8AtCaM1acOdOc25w= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781154085; c=relaxed/simple; bh=CRhjsZHkD7Sl441bFPGjztZUbbEF7q5Uy9WgqxTnHGE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JZojHxfCu0JV6j33Rfjs5ytMH8BTxIADBQ8RDihc8D19N1850ceofuFuLJTQNl3bHWAOAt52sDl8ts1MDN1bAqBkeYdhCHv+0tJhUnepXyV4JP6Wsc8x/aMAbwkSVXBp2xv3T/T7a4KwIS4OYY23qhygXQp9RYAoik2qZb9XmHU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=LCNBQAjE; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=cw/UJUWH; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="LCNBQAjE"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="cw/UJUWH" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65B0NT3V3202751 for ; Thu, 11 Jun 2026 05:01:14 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= xQrbnqb3JAm20jBiC9iPeFLBZRp3ucGiH/GJ4sUF6wE=; b=LCNBQAjEvlRnnjWD y9xsVWkdCTRs1AHN0WzK/kd7rSL8Sfw/6RBbLUiGdQjMlkieEkZu3kmzRIlNlwg2 mco3OACnHkDIwZbUmQ97bn0WC8l9GIIB14mOMbKlmqdDm1A8F3Cw+z6ZXjLNoEHd dkU9SzsS3f9YRt08rRqSy8NqnctmEZi2NXU3K5Vjop6H2CuF0d6YnSJ9YRMAlooY FX2ggmQ7mU1YJGqtkq9McMpU5vKFEQcP8iOTxgjpXW1ZVUJrhJmGw1OBlJb5qw7r fn9fy0K7nRZHTNMPI59PmEqfMP6DILZ1Uu2hGgP7c9X5Ad+3RO53BeXKmKhNxCdk 6pgx0w== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4eqe6thpey-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 11 Jun 2026 05:01:13 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-2bf55c3f44aso4735965ad.0 for ; Wed, 10 Jun 2026 22:01:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1781154073; x=1781758873; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=xQrbnqb3JAm20jBiC9iPeFLBZRp3ucGiH/GJ4sUF6wE=; b=cw/UJUWHyF3HGpWA6r8ocKfc+Ql354KwGC1rSMuFkEij1qjo89eYMrr4IWqfpq07Vt Eee5bXkd4xTE2fSqc5DvpAnH5BXWRVNt6AYnrsV9jyvthuy7rRoqRkiHIXK0K947JiEm xXs/feQmPKEFZDFbnfS9R9n43U7SzQd04kEd8Ncu3NVv4sVKHWGciaUUVjDuRnoJev7I a3GbynlK4YE1TSt5xv8KrZxIIbVGFsBW/KeyuU5Px6wvkX4m8Fakp0/7bIaspXDRrWNm 4j2YAYNVhAut4K5RtN1/J2ZJwOHJc5GbyT+FnpdFK7p4lTRamtLNJeylFBno8tgP0iCS 3AeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781154073; x=1781758873; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=xQrbnqb3JAm20jBiC9iPeFLBZRp3ucGiH/GJ4sUF6wE=; b=RTAHscstNr9E3+4ExN225ZVm8CHqzfHKC3GHJePVwdiS1RkCyuaGs0dZWwHMk+SlFJ Z2wNv1fiK6z5mS7v9P41EmQ2tPEXiGwlYJuZHNDwj1nmt3Fd08SH723GynvL8SFEYxDE kwajChT57Pw6ocaQQvuXnk9Jt+uPSm1tmVtXoenOoRJW6DawVgadQ6I6JVmVaYiwhL4T 6WQJBjzrq9UICSnyoxDUAIINvCypIhrUt3Np8jsIw3XOox+uxhldBNIxCvAAT29AymwI R6pfGkx4t/LXSR45VmDVbFgFOQpCCI1DoRkg0Pi8nr7lukk/PgMT1rQY27c73Hgydk0c 3DCA== X-Forwarded-Encrypted: i=1; AFNElJ9asYBJrqFowt7Z5Wy2mJz0z3BPV2AwFOCzA7WNrddFCVety7urJJ59X0d/HX0QJ5V7WmGd7Pbf4iT/RBE=@vger.kernel.org X-Gm-Message-State: AOJu0YwuimUCcNTdg3gf4S+PRiOIHqEoxHO2xhpxxQrPGNS4l4hnYyeA gGqCOIGLBo5RUg1qjA2vItbyb6MQJCCel6qMz3+w6beFYQSS5KgELmHxb5QqyMEmTrxKHAmJWVk S1tpa42jRXza0RF8feO9fIB3aUxBjzjHqogc6ExFHCoXcpNJ1khqDGEqql9uTegVQwfY= X-Gm-Gg: Acq92OFBpt6v0kGeAPfSNl5gNbcgSdoo+Ib66n3WHYwLSViT7gYmgwrIKquIWf5sZJs mov5q8zcBe/6sbkLQHGTeYUmrhFb+zj5UDgiiGCX9f0YOZENHLXUtw8LvEH8Hl3YEduz+P0kilG crazdBMkyiroJYqLUz+LkxuXRN0/N/tG8Wew3z38R3NtGdqy9bNEN9+Httu9PDb/vppzAoDcX3c p5GTU1YzQm83IPSUa/yQbgFnK4xYS2q5e5N0mbSPraik6rd9FJnGuJZkEPlu+a6nY4w6mJ5Z1+3 faC48B4Ug9zrRMVLUjJs8JAXIFsbJpXbGqfVB8QNer2QJJp+akZViniLDNSopqAZ/wYX91Ok/Eq GOWllgg/tWQt3DWTbPkclDnNczuK5V7L1gSf6yNnlPeaVnv5i2Y/iEh61UJvkt403i9s= X-Received: by 2002:a17:903:3d07:b0:2c0:a858:8128 with SMTP id d9443c01a7336-2c2f57ae62cmr10413205ad.1.1781154072918; Wed, 10 Jun 2026 22:01:12 -0700 (PDT) X-Received: by 2002:a17:903:3d07:b0:2c0:a858:8128 with SMTP id d9443c01a7336-2c2f57ae62cmr10412925ad.1.1781154072453; Wed, 10 Jun 2026 22:01:12 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c164f8bc5asm276188335ad.27.2026.06.10.22.01.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2026 22:01:12 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:11 +0530 Subject: [PATCH v2 35/37] arm64: dts: qcom: sm8650: Move PCIe phy and GPIOs to root port node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20260611-wake-v2-35-2744251b1181@oss.qualcomm.com> References: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com> In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , cros-qcom-dts-watchers@chromium.org, Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krishna Chaitanya Chundru , Krishna Chaitanya Chundru X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781153929; l=6180; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=CRhjsZHkD7Sl441bFPGjztZUbbEF7q5Uy9WgqxTnHGE=; b=AsZHzER8Ew0hYGscBoraPzd15cf9MuBuhuF3A0BL6Ws0y+3do/eDZR1XHkYy9AMxh0Fu3Quee 1F4stMs4BpxBXICUfvTYf6kUVrxNHhifr14aZsgu1NW4/YC1/dO72Sk X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjExMDA0NiBTYWx0ZWRfX3x01nH4QHg7s iVOkGgS4/oNIjiUlbLwWDHzTExqZFldT94zvypFFEoJk3Oy1hFKd+SCkhhf4cvMBXvkM/kn4wUs 5fTudd5vOWyy87z11g5RrenT936VCHGWLbbq/MXHt6tFWmpRnB8TQ9ysBP9Sr3AnkvSnRMIjg+0 k9GTpULc+V3j1ZtPxtoLWYQknWE4NRMUQ1dVoPksp3IHa4bAie65hNAhs717vK9nWdDN1rs6xVE EWYYNkf2BADJTBybVP+YKJG2W0oa/0FeTzcO6zTKae0vLCqLd4EmNZelI/uDzYvfx2z+AbNtfrU BTC3fIzRjQgMf57+W236dKy3jo8nEnjSTmx7WWnkE8GcXofn28WRiWyhVKkWnlP6txufRrkoykD wTPhnzqy8lnZ9Qpa9MxUgvPn/pN8YvPLZre2QESpCYvWrfEei+hwwpE/tA4zP/nzaJfj+G72V1j fnry0K4YqkueDl4YUIw== X-Proofpoint-Spam-Info: AW1haW4tMjYwNjExMDA0NiBTYWx0ZWRfX/Bcp00AauCN3 s1flyp0y8uhL8zu7RISmDlYWgoeb5dnfJFyP98Lb8ZUrbl0ePWTHvTol0DZb6zXZ+oHtAw+46Wi K9OA1LgpvZQR7ovfm3WfF7uMtjaMmg8= X-Authority-Analysis: v=2.4 cv=AaiB2XXG c=1 sm=1 tr=0 ts=6a2a4119 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=PQP5rm17eCTiIiCJsb4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-ORIG-GUID: 269pJRT-W4JbCVdcwIY47DaXgTNGQMXL X-Proofpoint-GUID: 269pJRT-W4JbCVdcwIY47DaXgTNGQMXL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-11_01,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 adultscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606110046 The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to the existing pcieport0 and pcie1_port0, allowing board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts | 14 ++++++++------ arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 14 ++++++++------ arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 16 ++++++++++------ arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 ++++------ 5 files changed, 33 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts index 2123312d88f6..74a286bf7696 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts @@ -1074,9 +1074,6 @@ &mdss_dp0_out { }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -1084,6 +1081,9 @@ &pcie0 { }; &pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; @@ -1108,15 +1108,17 @@ &pcie0_phy { }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &pcie1_port0 { /* Renesas μPD720201 PCIe USB3.0 HOST CONTROLLER */ usb-controller@0 { diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index 775ce9f2dba0..02f8760212a9 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -942,9 +942,6 @@ &mdss_dp0 { }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -952,6 +949,9 @@ &pcie0 { }; &pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; @@ -976,15 +976,17 @@ &pcie0_phy { }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l3e_0p9>; vdda-pll-supply = <&vreg_l3i_1p2>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index 8cc0d2cb3515..08107a559292 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -642,15 +642,17 @@ &mdss_dsi0_phy { }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l1i_0p88>; vdda-pll-supply = <&vreg_l3i_1p2>; @@ -659,15 +661,17 @@ &pcie0_phy { }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l3e_0p9>; vdda-pll-supply = <&vreg_l3i_1p2>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index c302996a7857..a18c01a48e4f 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -936,9 +936,6 @@ &mdss_dp0 { }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -946,6 +943,9 @@ &pcie0 { }; &pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 1604bc8cff37..fc6fc4d7e39d 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3644,9 +3644,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, num-lanes = <2>; bus-range = <0 0xff>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>, @@ -3716,6 +3713,8 @@ pcieport0: pcie@0 { #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie0_phy>; }; }; @@ -3837,9 +3836,6 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, num-lanes = <2>; bus-range = <0 0xff>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - dma-coherent; #address-cells = <3>; @@ -3925,6 +3921,8 @@ pcie1_port0: pcie@0 { #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie1_phy>; }; }; -- 2.34.1