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Wed, 10 Jun 2026 22:01:16 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c164f8bc5asm276188335ad.27.2026.06.10.22.01.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2026 22:01:16 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:12 +0530 Subject: [PATCH v2 36/37] arm64: dts: qcom: kodiak: Move PCIe phy and GPIOs to root port node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260611-wake-v2-36-2744251b1181@oss.qualcomm.com> References: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com> In-Reply-To: <20260611-wake-v2-0-2744251b1181@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , cros-qcom-dts-watchers@chromium.org, Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krishna Chaitanya Chundru , Krishna Chaitanya Chundru X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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Move phys from the controller to pcie0_port and pcie1_port0, and move perst-gpios/wake-gpios from the &pcie0/&pcie1 controller overrides to the respective &pcie0_port/&pcie1_port0 nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 10 ++++------ arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts | 15 ++++++++++----- arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 16 ++++++++++------ .../dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso | 4 ++-- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 4 ++-- .../boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts | 14 ++++++++------ .../arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts | 16 ++++++++++------ arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 5 ++++- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 5 ++++- 9 files changed, 54 insertions(+), 35 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index 988ca5f7c8a0..52887643e1a4 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -2286,9 +2286,6 @@ pcie0: pcie@1c00000 { power-domains = <&gcc GCC_PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - pinctrl-names = "default"; pinctrl-0 = <&pcie0_clkreq_n>; dma-coherent; @@ -2300,6 +2297,8 @@ pcie0_port: pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie0_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -2416,9 +2415,6 @@ pcie1: pcie@1c08000 { power-domains = <&gcc GCC_PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - pinctrl-names = "default"; pinctrl-0 = <&pcie1_clkreq_n>; @@ -2434,6 +2430,8 @@ pcie1_port0: pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie1_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts index b1ad1d7c346a..92023aac967d 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts @@ -545,15 +545,17 @@ &mdss_dp_out { }; &pcie0 { - perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>; pinctrl-names = "default"; status = "okay"; }; +&pcie0_port { + reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l10c_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; @@ -562,8 +564,6 @@ &pcie0_phy { }; &pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>; pinctrl-names = "default"; @@ -572,6 +572,11 @@ &pcie1 { status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l10c_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts index 3a9fbef89aff..d0639eea398e 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts @@ -522,15 +522,17 @@ &lpass_va_macro { }; &pcie0 { - perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>; pinctrl-names = "default"; status = "okay"; }; +&pcie0_port { + reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l10c_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; @@ -539,9 +541,6 @@ &pcie0_phy { }; &pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>; pinctrl-names = "default"; @@ -559,6 +558,11 @@ &pcie1 { status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l10c_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso index 83908db335af..8e65a63a533f 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -49,8 +49,6 @@ st33htpm0: tpm@0 { }; &pcie0 { - perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>; pinctrl-names = "default"; @@ -75,6 +73,8 @@ &pcie0_phy { }; &pcie0_port { + reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index e393ccf1884a..3a7998f7ca55 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -824,8 +824,6 @@ &mdss_edp_phy { }; &pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>; pinctrl-names = "default"; @@ -850,6 +848,8 @@ &pcie1_phy { }; &pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + pcie@0,0 { compatible = "pci1179,0623"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts index e0275430ef82..65687a6aeb6f 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts @@ -684,9 +684,6 @@ &mdss_dsi_phy { }; &pcie0 { - perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>; @@ -695,6 +692,11 @@ &pcie0 { status = "okay"; }; +&pcie0_port { + reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l10c_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; @@ -703,9 +705,6 @@ &pcie0_phy { }; &pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>; @@ -732,6 +731,9 @@ &pcie1_phy { }; &pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; + pcie@0,0 { compatible = "pci1179,0623"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts index 681a9ff5ef77..e5c549c794a9 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts @@ -812,9 +812,6 @@ &mdss_dsi_phy { }; &pcie0 { - perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>; @@ -823,6 +820,11 @@ &pcie0 { status = "okay"; }; +&pcie0_port { + reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l10c_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; @@ -831,9 +833,6 @@ &pcie0_phy { }; &pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>; @@ -842,6 +841,11 @@ &pcie1 { status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l10c_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 5c5e4f1dd221..9198377c2a8c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -472,10 +472,13 @@ &pcie1 { pinctrl-names = "default"; pinctrl-0 = <&pcie1_clkreq_n>, <&ssd_rst_l>, <&pe_wake_odl>; - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&pp3300_ssd>; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; +}; + &pm8350c_pwm { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 8cac4ce9c851..655192adbd5d 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -418,7 +418,6 @@ &lpass_va_macro { &pcie1 { status = "okay"; - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&nvme_3v3_regulator>; @@ -426,6 +425,10 @@ &pcie1 { pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { status = "okay"; -- 2.34.1