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Thu, 11 Jun 2026 02:09:45 -0700 (PDT) From: fuqiang wang To: Marc Zyngier , Oliver Upton , Zenghui Yu , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev Cc: dongxu zhang , wangfuqiang49 , fuqiang wang Subject: [PATCH 1/2] arm64: Add MIDR_EL1 RES1 definitions Date: Thu, 11 Jun 2026 17:09:33 +0800 Message-ID: <20260611090934.84469-2-fuqiang.wng@gmail.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20260611090934.84469-1-fuqiang.wng@gmail.com> References: <20260611090934.84469-1-fuqiang.wng@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit MIDR_EL1 bit 31 is RES1. Add named definitions for the bit. Signed-off-by: fuqiang wang --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 7b518e81dd15..4322b219f79a 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -39,6 +39,8 @@ #define MIDR_IMPLEMENTOR_MASK (0xffU << MIDR_IMPLEMENTOR_SHIFT) #define MIDR_IMPLEMENTOR(midr) \ (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) +#define MIDR_RES1_SHIFT 31 +#define MIDR_RES1_MASK (1 << MIDR_RES1_SHIFT) #define MIDR_CPU_MODEL(imp, partnum) \ ((_AT(u32, imp) << MIDR_IMPLEMENTOR_SHIFT) | \ -- 2.47.0