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The hardware supports averaging 2, 4, 8, or 16 samples, plus a ratio of 1 (no averaging). Temperature and supply channels share oversampling configuration at the type level (all temperature channels share one ratio, all supply channels share another), exposed through info_mask_shared_by_type. The hardware encoding uses sample_count / 2 in a 4-bit field within the CONFIG register. Per-channel averaging enable registers must also be updated to activate or deactivate averaging. Signed-off-by: Salih Erim --- Changes in v6: - Fix FIELD_PREP indentation in sysmon_osr_write (Andy) - unsigned int for loop index in sysmon_write_raw (Andy) Changes in v5: - Remove unneeded parentheses in i * SYSMON_REG_STRIDE (Andy) - Use struct regmap *map local variable in sysmon_set_avg_enable (Andy) - switch instead of redundant if/if on channel_type (Andy) - Add CONFIG register readback fence after oversampling update to prevent NoC bus hang from posted writes (found during hardware stress testing) Changes in v4: - Return directly from sysmon_set_avg_enable calls, remove else after early returns, drop unreachable return 0 (Jonathan) - Rename mask defines to SYSMON_CONFIG_SUPPLY_OSR and SYSMON_CONFIG_TEMP_SAT_OSR (Jonathan) - Drop "bits X:Y" from GENMASK comments (Jonathan) - Blank lines after if (ret) return ret blocks (Jonathan) - Move oversampling read inside guard(mutex) scope Changes in v3: - No changes Changes in v2: - EN_AVG per-channel bitmask registers written with all-ones instead of boolean 1 when oversampling is enabled - EN_AVG write errors propagated to userspace - Oversampling limited to satellite temp and supply channels; static temp channels do not participate - Oversampling exposes actual sample counts (1,2,4,8,16) to userspace with internal HW register translation - write_raw_get_fmt returns IIO_VAL_INT for oversampling ratio - HW encoding documented (sample_count/2, not log2) - oversampling_avail is const int[] (type match fix) drivers/iio/adc/versal-sysmon-core.c | 147 ++++++++++++++++++++++++++- drivers/iio/adc/versal-sysmon.h | 17 ++++ 2 files changed, 163 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/versal-sysmon-core.c b/drivers/iio/adc/versal-sysmon-core.c index 20fd3a87d44..fa8f0dc868a 100644 --- a/drivers/iio/adc/versal-sysmon-core.c +++ b/drivers/iio/adc/versal-sysmon-core.c @@ -26,6 +26,12 @@ #include "versal-sysmon.h" +/* + * Oversampling ratio values exposed to userspace via IIO. + * Actual number of samples averaged: 1=none, 2=2x, 4=4x, 8=8x, 16=16x. + */ +static const int sysmon_oversampling_avail[] = { 1, 2, 4, 8, 16 }; + /* OT and TEMP hysteresis mode bits in SYSMON_TEMP_EV_CFG */ #define SYSMON_OT_HYST_MASK BIT(0) #define SYSMON_TEMP_HYST_MASK BIT(1) @@ -196,6 +202,12 @@ static int sysmon_read_raw(struct iio_dev *indio_dev, guard(mutex)(&sysmon->lock); + if (mask == IIO_CHAN_INFO_OVERSAMPLING_RATIO) { + *val = (chan->type == IIO_TEMP) ? sysmon->temp_oversampling : + sysmon->supply_oversampling; + return IIO_VAL_INT; + } + switch (chan->type) { case IIO_TEMP: if (mask == IIO_CHAN_INFO_SCALE) { @@ -515,6 +527,126 @@ static int sysmon_write_event_value(struct iio_dev *indio_dev, } } +static int sysmon_set_avg_enable(struct sysmon *sysmon, + u32 base, u32 count, u32 val) +{ + struct regmap *map = sysmon->regmap; + int ret; + + for (unsigned int i = 0; i < count; i++) { + ret = regmap_write(map, base + i * SYSMON_REG_STRIDE, val); + if (ret) + return ret; + } + + return 0; +} + +static int sysmon_osr_write(struct sysmon *sysmon, int channel_type, int val) +{ + /* + * HW register encoding is sample_count / 2: + * 0=none, 1=2x, 2=4x, 4=8x, 8=16x (not log2-based). + */ + int hw_val = val >> 1; + unsigned int readback; + int ret; + + switch (channel_type) { + case IIO_TEMP: + ret = regmap_update_bits(sysmon->regmap, SYSMON_CONFIG, + SYSMON_CONFIG_TEMP_SAT_OSR, + FIELD_PREP(SYSMON_CONFIG_TEMP_SAT_OSR, hw_val)); + if (ret) + return ret; + + /* + * Readback fence: the SysMon CONFIG register resides in the + * PMC domain behind the NoC. A posted write may not reach the + * hardware before the next MMIO access. Reading the register + * back forces the interconnect to complete the write, preventing + * a bus hang on the subsequent access. + */ + regmap_read(sysmon->regmap, SYSMON_CONFIG, &readback); + + return sysmon_set_avg_enable(sysmon, SYSMON_TEMP_EN_AVG_BASE, + SYSMON_TEMP_EN_AVG_COUNT, + hw_val ? ~0U : 0); + case IIO_VOLTAGE: + ret = regmap_update_bits(sysmon->regmap, SYSMON_CONFIG, + SYSMON_CONFIG_SUPPLY_OSR, + FIELD_PREP(SYSMON_CONFIG_SUPPLY_OSR, hw_val)); + if (ret) + return ret; + + /* Readback fence -- see above */ + regmap_read(sysmon->regmap, SYSMON_CONFIG, &readback); + + return sysmon_set_avg_enable(sysmon, SYSMON_SUPPLY_EN_AVG_BASE, + SYSMON_SUPPLY_EN_AVG_COUNT, + hw_val ? ~0U : 0); + default: + return -EINVAL; + } +} + +static int sysmon_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + struct sysmon *sysmon = iio_priv(indio_dev); + unsigned int i; + int ret; + + if (mask != IIO_CHAN_INFO_OVERSAMPLING_RATIO) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(sysmon_oversampling_avail); i++) { + if (val == sysmon_oversampling_avail[i]) + break; + } + if (i == ARRAY_SIZE(sysmon_oversampling_avail)) + return -EINVAL; + + guard(mutex)(&sysmon->lock); + + ret = sysmon_osr_write(sysmon, chan->type, val); + if (ret) + return ret; + + if (chan->type == IIO_TEMP) + sysmon->temp_oversampling = val; + else + sysmon->supply_oversampling = val; + + return 0; +} + +static int sysmon_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + long mask) +{ + if (mask == IIO_CHAN_INFO_OVERSAMPLING_RATIO) + return IIO_VAL_INT; + + return -EINVAL; +} + +static int sysmon_read_avail(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + const int **vals, int *type, + int *length, long mask) +{ + if (mask != IIO_CHAN_INFO_OVERSAMPLING_RATIO) + return -EINVAL; + + *vals = sysmon_oversampling_avail; + *type = IIO_VAL_INT; + *length = ARRAY_SIZE(sysmon_oversampling_avail); + + return IIO_AVAIL_LIST; +} + static int sysmon_read_label(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, char *label) @@ -527,6 +659,9 @@ static int sysmon_read_label(struct iio_dev *indio_dev, static const struct iio_info sysmon_iio_info = { .read_raw = sysmon_read_raw, + .write_raw = sysmon_write_raw, + .write_raw_get_fmt = sysmon_write_raw_get_fmt, + .read_avail = sysmon_read_avail, .read_label = sysmon_read_label, .read_event_config = sysmon_read_event_config, .write_event_config = sysmon_write_event_config, @@ -826,6 +961,10 @@ static int sysmon_parse_fw(struct iio_dev *indio_dev, struct device *dev, .indexed = 1, .address = reg, .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), + .info_mask_shared_by_type = + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .info_mask_shared_by_type_available = + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), .event_spec = irq > 0 ? sysmon_supply_events : NULL, .num_event_specs = irq > 0 ? @@ -857,7 +996,11 @@ static int sysmon_parse_fw(struct iio_dev *indio_dev, struct device *dev, .address = SYSMON_TEMP_SAT_BASE + (reg - 1) * SYSMON_REG_STRIDE, .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), - .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), + .info_mask_shared_by_type = + BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .info_mask_shared_by_type_available = + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), .datasheet_name = label, }; } @@ -904,6 +1047,8 @@ int sysmon_core_probe(struct device *dev, struct regmap *regmap) sysmon = iio_priv(indio_dev); sysmon->regmap = regmap; + sysmon->temp_oversampling = 1; + sysmon->supply_oversampling = 1; ret = devm_mutex_init(dev, &sysmon->lock); if (ret) diff --git a/drivers/iio/adc/versal-sysmon.h b/drivers/iio/adc/versal-sysmon.h index 2c6cea64ddf..c6b9e496c1c 100644 --- a/drivers/iio/adc/versal-sysmon.h +++ b/drivers/iio/adc/versal-sysmon.h @@ -23,11 +23,13 @@ struct regmap; #define SYSMON_IMR 0x0048 #define SYSMON_IER 0x004C #define SYSMON_IDR 0x0050 +#define SYSMON_CONFIG 0x0100 #define SYSMON_TEMP_MAX 0x1030 #define SYSMON_TEMP_MIN 0x1034 #define SYSMON_SUPPLY_BASE 0x1040 #define SYSMON_ALARM_FLAG 0x1018 #define SYSMON_ALARM_REG 0x1940 +#define SYSMON_SUPPLY_EN_AVG_BASE 0x1958 #define SYSMON_TEMP_TH_LOW 0x1970 #define SYSMON_TEMP_TH_UP 0x1974 #define SYSMON_OT_TH_LOW 0x1978 @@ -39,6 +41,7 @@ struct regmap; #define SYSMON_TEMP_MAX_MAX 0x1F90 #define SYSMON_STATUS_RESET 0x1F94 #define SYSMON_TEMP_SAT_BASE 0x1FAC +#define SYSMON_TEMP_EN_AVG_BASE 0x24B4 #define SYSMON_MAX_REG 0x24C0 /* NPI unlock value written to SYSMON_NPI_LOCK */ @@ -55,6 +58,16 @@ struct regmap; /* ISR/IMR temperature and OT alarm mask (bits 9:8) */ #define SYSMON_TEMP_INTR_MASK GENMASK(9, 8) +/* SYSMON_CONFIG: supply oversampling ratio */ +#define SYSMON_CONFIG_SUPPLY_OSR GENMASK(17, 14) + +/* SYSMON_CONFIG: temperature satellite oversampling ratio */ +#define SYSMON_CONFIG_TEMP_SAT_OSR GENMASK(27, 24) + +/* Per-channel averaging enable register counts */ +#define SYSMON_SUPPLY_EN_AVG_COUNT 5 +#define SYSMON_TEMP_EN_AVG_COUNT 2 + /* Supply voltage conversion register fields */ #define SYSMON_MANTISSA_MASK GENMASK(15, 0) #define SYSMON_FMT_MASK BIT(16) @@ -84,6 +97,8 @@ struct regmap; * @temp_hysteresis: cached DEVICE_TEMP hysteresis in millicelsius * @ot_hysteresis: cached OT hysteresis in millicelsius * @sysmon_unmask_work: re-enables events after alarm condition clears + * @temp_oversampling: current temp oversampling ratio + * @supply_oversampling: current supply oversampling ratio */ struct sysmon { struct regmap *regmap; @@ -104,6 +119,8 @@ struct sysmon { int temp_hysteresis; int ot_hysteresis; struct delayed_work sysmon_unmask_work; + unsigned int temp_oversampling; + unsigned int supply_oversampling; }; int sysmon_core_probe(struct device *dev, struct regmap *regmap); -- 2.48.1