From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B2BB3DB30A for ; Thu, 11 Jun 2026 23:45:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781221551; cv=none; b=kF1k1pZ2sxVCnEqYJg5I8q8B5puyi3yewIgYd3u1FgaMOSMuE+3++i0lZtzS+gfrrdfqaRxhkI1dBHyyjBgyv7aAxxt/3BDq9fK89RMwo696cfXPijMhzRrF/Qhhawqw1wDQqrB2PamNpB2/f/nAENsRy+YNpzhcs6nA/5DGF08= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781221551; c=relaxed/simple; bh=wy+5kI0dveBACR23utkY1IqEQo7BkKlp9zuSxmhVWxY=; h=From:Subject:Date:Message-Id:MIME-Version:Content-Type:To:Cc; b=CqjGTPdpoXOqQvErYCkCrojCxoAQE2U9iVk4/aKF8JqPzAfy0kZtPmjWGtmPNeOffaYf2N10lEWxJZyAo313tkc35FP88YgFAsuhc9rOuXXPwKiybqHgLhn/pZSF5NT5JjNabNJSYj22eYx3DiIHLdlK2wurlqQMnPigdXsGXkU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=CF46rZbX; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="CF46rZbX" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1781221543; bh=wy+5kI0dveBACR23utkY1IqEQo7BkKlp9zuSxmhVWxY=; h=From:Subject:Date:To:Cc:From; b=CF46rZbX76KJmTbFU3cuopRVOvxjTnkPXftdfiTaarMmyx3NT/UNn/CQ6+quU1+Gc omcyp3tXmOFDhcdWTJyZSltnGH8dmmIyDxj7bbLdj9zIXFwS4dr34WfwIkGiFo4jG1 ro3wY6HhHGSR0n60yok3CzPGjiKvEKel/9Xvw7f9QXjCsl0Na5Jym6QVFDgnf3Im4l N6vo60omXHcFGUF4yYaiAhLWFFahbZdBbUeKj8XpW0cmmhv7Tk+TORQ7KoYmOTf9ME n8D/zxtjZcgcJ3q0tDXOw/R+/LvyzMhAJfQaKJDfbkK5Pnax1l1lczWoVXJ5bQLWh2 udpdxsGhCoabg== Received: from localhost (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 2C53617E0615; Fri, 12 Jun 2026 01:45:43 +0200 (CEST) From: Cristian Ciocaltea Subject: [PATCH v4 0/8] phy: rockchip: samsung-hdptx: Clock fixes and API transition cleanups Date: Fri, 12 Jun 2026 02:45:19 +0300 Message-Id: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAAAAAAAC/3XNQQ6CMBAF0KuYrq1phzoFV97DuIDSSiNS0pIGQ 7i7hQ2J4vL/yX8zkaC91YFcDhPxOtpgXZeCOB6IasruoamtUybAABmApE3dDyNV7ZMaO+pAhRS AmIHJEUha9V6vhzS63VNubBicf68PIl/a/1bklFFTFLkBiVAzc1WubcvK+fKk3IssXoTNOHP+a 0AyEIUWPJOFKqs9I9sM3DOyxZAVr5hiTHP8NuZ5/gB0k7zcOgEAAA== X-Change-ID: 20260227-hdptx-clk-fixes-47426632f862 To: Vinod Koul , Neil Armstrong , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Thomas_Niederpr=C3=BCm?= , Simon Wright , Sashiko X-Mailer: b4 0.15.2 This series provides a set of bug fixes and cleanups for the Rockchip Samsung HDPTX PHY driver. The first part of the series addresses clock rate calculation and synchronization issues. Specifically, it fixes edge cases where the PHY PLL is pre-programmed by an external component (like a bootloader) or when changing the color depth (bpc) while keeping the modeline constant. Because the Common Clock Framework .set_rate() callback might not be invoked if the pixel clock remains unchanged, this previously led to out-of-sync states between CCF and the actual HDMI PHY configuration. The second part focuses on code cleanups and modernizing the register access. Now that dw_hdmi_qp driver has fully switched to using phy_configure(), we can drop the deprecated TMDS rate setup workarounds and the restrict_rate_change flag logic. Finally, it refactors the driver to consistently use standard bitfield macros. Signed-off-by: Cristian Ciocaltea --- Changes in v4: - Added new patches to address new findings from Sashiko: * Prevent divide-by-zero when computing clk rate * Fix rate recalculation for 3.2GHz FRL - Updated patch "Consistently use bitfield macros" to handle a few more bit operations - Link to v3: https://patch.msgid.link/20260611-hdptx-clk-fixes-v3-0-67b1b0c00e16@collabora.com Changes in v3: - Replaced div_u64() with DIV_ROUND_CLOSEST_ULL() in Patch 1 (Sashiko) - Fixed theoretical usage_count unbalanced issue in Patch 2 (Sashiko) - Rebased series onto latest phy/next - Link to v2: https://patch.msgid.link/20260511-hdptx-clk-fixes-v2-0-664e41379cab@collabora.com Changes in v2: - Collected Tested-by tags from Thomas and Simon - Fixed a typo in commit description of patch 1 - Added a comment in patch 2 explaining why PLL config errors are ignored for rk_hdptx_phy_consumer_get() - Added a missed FIELD_GET conversion for lcpll_hw.pms_sdiv in patch 6 - Rebased onto latest phy/fixes - Link to v1: https://lore.kernel.org/r/20260227-hdptx-clk-fixes-v1-0-f998f2762d0f@collabora.com --- Cristian Ciocaltea (8): phy: rockchip: samsung-hdptx: Fix rate recalculation for high bpc phy: rockchip: samsung-hdptx: Prevent divide-by-zero when computing clk rate phy: rockchip: samsung-hdptx: Fix rate recalculation for 3.2GHz FRL phy: rockchip: samsung-hdptx: Handle uncommitted PHY config changes phy: rockchip: samsung-hdptx: Drop TMDS rate setup workaround phy: rockchip: samsung-hdptx: Drop restrict_rate_change handling phy: rockchip: samsung-hdptx: Simplify GRF access with FIELD_PREP_WM16() phy: rockchip: samsung-hdptx: Consistently use bitfield macros drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 266 +++++++++++----------- 1 file changed, 130 insertions(+), 136 deletions(-) --- base-commit: 293e19f416fa3f233a2fb013258f7abcb39ad6ed change-id: 20260227-hdptx-clk-fixes-47426632f862