From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C7443D9DD3 for ; Thu, 11 Jun 2026 23:45:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781221552; cv=none; b=Nsdw0//7qu9lb0EGVSUqt7dx0bZgVgWWxKmMDTwOIsw4WNdteyJohL0Tcq20I7jac6cWQDtYALdFqKnfz84KuoQEUqtO0Uig47ydSWt/ZyAGsVeYD/kPpwqYwpaGl1wQavS+W8fwpjmhwYzv5PMHXcZUGaun1Fq7sfXDYQe1N/4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781221552; c=relaxed/simple; bh=mMmN5c98AYlSbEtpnRmRYuYBWUBFkWC7EXBgNfEYdGA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=o6D5MDZEn6bGtEzsx2QvvPcF+fken/b0gz4Pw61riwa6EoEO4oCtS4dOGHr+KGdBGKjpw1NP6btzD9T27Gd8UtqZD2tdBlx2xqWVN0Jd5YFIpGeyHdxyB+RujdfA3wZ873SP0IN0by3jUoPxItQoooTD502TvMR1sDipUqbwwYE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=IKb/8iW0; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="IKb/8iW0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1781221545; bh=mMmN5c98AYlSbEtpnRmRYuYBWUBFkWC7EXBgNfEYdGA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=IKb/8iW0KR4HQAdWnwDM0XtSBzPAQyTMVXYiZ4jSEci4zymshCVCkjv7w9prf9neO gC+rl80PFEkpMqkZ5XqYgM72nfWbOJbZ7e0Qp/hhmMlTiAWuGbDskeTanG3RAm2lXh iyJVqkNse3LiLpPXmTDKOI8bZp6zlDbdMT/hzaMYAPQ8Q/vFnzlhN9ujgjyPdE/E9x 2Z4eXHDGaP4souQZ29b8IlMJ95mD8lL/r19Z4O8BY55PU385HybmW9UG4AXdj8fmmu rEiUk4MyKxHHwIl/BTP/bmg88dqHEsKbzu/Y+89K6XrxaeviJ585SwZO52wOlF/wx6 guUAvn0PIHrEQ== Received: from localhost (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 917F117E0A49; Fri, 12 Jun 2026 01:45:45 +0200 (CEST) From: Cristian Ciocaltea Date: Fri, 12 Jun 2026 02:45:22 +0300 Subject: [PATCH v4 3/8] phy: rockchip: samsung-hdptx: Fix rate recalculation for 3.2GHz FRL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260612-hdptx-clk-fixes-v4-3-ce5e1d456cda@collabora.com> References: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> In-Reply-To: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> To: Vinod Koul , Neil Armstrong , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Sashiko X-Mailer: b4 0.15.2 rk_hdptx_phy_clk_calc_rate_from_pll_cfg() is currently unable to handle cascade mode for the 3.2GHz FRL operating mode, as it relies solely on LCPLL_LCVCO_MODE_EN_MASK to determinate the rate from the rk_hdptx_frl_lcpll_cfg array. Since there is no entry for this particular rate, the function returns 0. This is the only rate which requires LC_REF_CLK_SEL to be set in GRF_HDPTX_CON0, hence extend the FRL matching accordingly. Reported-by: Sashiko Closes: https://sashiko.dev/#/patchset/20260611-hdptx-clk-fixes-v3-0-67b1b0c00e16@collabora.com?part=1 Fixes: de5dba833118 ("phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support") Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 33 ++++++++++++++++------- 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c index 8c044381b83a..b210c1a88b25 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -2206,16 +2206,31 @@ static u64 rk_hdptx_phy_clk_calc_rate_from_pll_cfg(struct rk_hdptx_phy *hdptx) return 0; lcpll_hw.sdc_n = (val & LCPLL_SDC_N_MASK) >> 1; - for (i = 0; i < ARRAY_SIZE(rk_hdptx_frl_lcpll_cfg); i++) { - const struct lcpll_config *cfg = &rk_hdptx_frl_lcpll_cfg[i]; + ret = regmap_read(hdptx->grf, GRF_HDPTX_CON0, &val); + if (ret) + return 0; - if (cfg->pms_mdiv == lcpll_hw.pms_mdiv && - cfg->pms_sdiv == lcpll_hw.pms_sdiv && - cfg->sdm_num_sign == lcpll_hw.sdm_num_sign && - cfg->sdm_num == lcpll_hw.sdm_num && - cfg->sdm_deno == lcpll_hw.sdm_deno && - cfg->sdc_n == lcpll_hw.sdc_n) - return cfg->rate; + if (val & LC_REF_CLK_SEL) { + if (lcpll_hw.pms_mdiv == 0x6b && + lcpll_hw.sdm_num_sign == 0x01 && + lcpll_hw.sdm_num == 0x02 && + lcpll_hw.sdm_deno == 0x09 && + lcpll_hw.sdc_n == FIELD_GET(LCPLL_SDC_N_MASK, 0x02)) + return FRL_8G4L_RATE; + } else { + const struct lcpll_config *cfg; + + for (i = 0; i < ARRAY_SIZE(rk_hdptx_frl_lcpll_cfg); i++) { + cfg = &rk_hdptx_frl_lcpll_cfg[i]; + + if (cfg->pms_mdiv == lcpll_hw.pms_mdiv && + cfg->pms_sdiv == lcpll_hw.pms_sdiv && + cfg->sdm_num_sign == lcpll_hw.sdm_num_sign && + cfg->sdm_num == lcpll_hw.sdm_num && + cfg->sdm_deno == lcpll_hw.sdm_deno && + cfg->sdc_n == lcpll_hw.sdc_n) + return cfg->rate; + } } dev_dbg(hdptx->dev, "%s no FRL match found\n", __func__); -- 2.54.0