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Fri, 12 Jun 2026 02:57:51 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Fri, 12 Jun 2026 02:57:49 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Fri, 12 Jun 2026 02:57:49 -0700 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id A3EB23F7040; Fri, 12 Jun 2026 02:57:47 -0700 (PDT) From: Geetha sowjanya To: , , , CC: , , , Subject: [PATCH v2 0/3] perf: marvell: LLC-TAD PMU MPAM filtering support Date: Fri, 12 Jun 2026 15:27:43 +0530 Message-ID: <20260612095746.19679-1-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjEyMDA5MCBTYWx0ZWRfX8orRE9Qu8ZtH 1qMvX4tzVG6OeL8pJndA2WjFBcpy7yqDIWp5UYRbIVsqLgHFoa5BjKE4nal0OuQTJFHnmqqKpMb CNtLwbjb/k6nHwtNHSXPflrgpzrWCUxN84widfQ8bFiIygsEoy93G/+kHx4KNo/VkaftWGl0oXH dAHmx00Toigyl/4t9Bm8i2B/uKmXbRlpN/Rp9oxrFleZkyjsmP9YkF5YX2odssnbVe5PbNATy5O hXn9D2mhPCBH97OE79slq2OkMAa1VwzLkWrUKwff+MBmfgZW+PcZWThdTA+tGWt1xk5HiCtlJJL K5U1n6DAW6/vxDRF30wk31LjIZgC7I3wwwUaanv9z3oBQoCFL0GZHhrvUUyWdVmHMQrCOPIFj0H 13QhCkxHT350VE/lfyS9qMsFZ4MVDDhcWytDZKIL/83liQhok44waLl9s08UchEFeLpeOnPQDvq N/1yTiSFysH5aHW3/VA== X-Authority-Analysis: v=2.4 cv=GoByPE1C c=1 sm=1 tr=0 ts=6a2bd81f cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=FelO9ux0wxsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=qit2iCtTFQkLgVSMPQTB:22 a=M5GUcnROAAAA:8 a=KMVilSr8rocH2AwasoUA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjEyMDA5MCBTYWx0ZWRfXzbl0NpO/5elC y0L1rzoTwwa1ZnF6Cu5p/5Hv+OCl1iBCd3i3RPRwvlvSyPxwtKRlTSuxhaCT2PJlEJOwb/OQfmp VTWXXx027PnkN/CxbYJMiQAlkJmkhOI= X-Proofpoint-GUID: KtVaQ1yIH1D98X_-_s8nIePreeDEcsUN X-Proofpoint-ORIG-GUID: KtVaQ1yIH1D98X_-_s8nIePreeDEcsUN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-12_01,2026-06-11_01,2025-10-01_01 This series extends the Marvell LLC-TAD PMU driver for CN10K and CN20K platforms by adding MPAM-based filtering support and introducing CN20K hardware support. Patch 1 adds optional MPAM partition-id (partid) filtering for the subset of events that support it. The partid and partid_en fields are exposed via the PMU format attribute, while platforms that do not support filtering continue to expose a reduced event set without these fields. This patch also includes several fixes and cleanups: - Avoid modifying platform_get_resource() bounds in-place - Validate the MMIO window size against tad-cnt - Correct ordering of perf registration and CPU hotplug with proper unwind - Align the filter-enable bit in config1 with the sysfs format (bit 9) Patch 2 adds support for the CN20K LLC-TAD PMU. Compared to CN10K, CN20K uses different PFC/PRF register offsets and introduces additional events. This patch: - Adds a CN20K (V3) profile with platform-specific register offsets - Extends the event map and hides CN20K-only events on CN10K - Implements CN20K-specific MPAM encoding for filtering - Ensures correct counter initialization using local64_set(prev_count) - Adds device discovery via OF and ACPI (MRVL000F) Patch 3 updates the Devicetree binding documentation to add support for "marvell,cn20k-tad-pmu" Changes since v1 ---------------- - config1: use bit 9 for MPAM filter enable consistently with partid_en in the PMU format; allow only bits 0..9 in event_init on CN10K/CN20K paths. - Hide V3-only sysfs events on V1. - Reset prev_count when starting counters after clearing hardware. - DT binding: explain non-fallback compatibles for CN10K vs CN20K. Tanmay Jagdale (1): perf: marvell: Add MPAM partid filtering to CN10K TAD PMU Geetha sowjanya (2): perf: marvell: Add CN20K LLC-TAD PMU support dt-bindings: perf: marvell: Extend CN10K TAD PMU binding for CN20K Signed-off-by: Geetha sowjanya -- 2.25.1