From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F16D3B5307 for ; Fri, 12 Jun 2026 16:05:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781280340; cv=none; b=qvmooBD97NXELEV08QvUjRtnOzrv/Y4uo1YOgi+14XdfPFRmGvZoG/kevN2wsrAczHtVE7Aly8HSom5NpFer95EEeZgxhuiOfNvziigXXfVx3HQXi47z43M5FgRfoiveoF2C+S0OkmZor+Kv6Xtp+dw1YShs2Q8sSku9E0FMnc8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781280340; c=relaxed/simple; bh=TK0PGmasHyJ32/3ieDgZWV5QGMlnegde2D8vp6zSXy8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=k4XOsKxiHz3p8Im8Ka1Py7WUwO/jxeNY/96a/lTEHigOdwJZ/DbPn/PzdYgBtBAVgzKS8vUe5odpygUnyXn70/Jz+6EKJa6vifraG1T/TBtaJZiN1BkthvEP74LupZrmehoJ8EGQ96wS+9F6+uqZCVABE7FTgQPdANUjjYQ8pBk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eiQZOLmY; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eiQZOLmY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BFDA21F000E9; Fri, 12 Jun 2026 16:05:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1781280339; bh=YP+kSiUsGoR6jpW1tZMHdPwHHVI5I8KcyWDllQljcpE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=eiQZOLmYqqA5ROZv4OGcZLCq7ljHkw/QkYeKayzGpwhABy6EHGFklnD+8sUWZrep8 0mMSZK75Rj9uBPtEbCzPEx/1VD9bBQV46br0uOkEiz8DwMcTUoKXvG06YFuSe85dJU u9pKg8wXclyOboHGCuPcCRzFT05gIAzzxwLD996kPrSBDDHvWJVZujqAhVJ3a2ZWzs Rb6fQ3t7fhT0OkemO35t5/+/qvM9btJuqxITP3Xvs9eFXUEzoOoNAKBMzHjjCYsbEs c/xTcOZzf3uVSjTsTiobqthK8pK1whLGQ1vvH7buwz1T4IAXBOhi9dBLULTCTjgrEx 4Yc4qVA6X6utw== From: Claudiu Beznea To: wsa+renesas@sang-engineering.com, tommaso.merciai.xr@bp.renesas.com, alexandre.belloni@bootlin.com, Frank.Li@nxp.com, p.zabel@pengutronix.de Cc: claudiu.beznea@kernel.org, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v4 12/16] i3c: renesas: Update HW registers after SW computations are done Date: Fri, 12 Jun 2026 19:04:54 +0300 Message-ID: <20260612160458.3102106-13-claudiu.beznea@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260612160458.3102106-1-claudiu.beznea@kernel.org> References: <20260612160458.3102106-1-claudiu.beznea@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Claudiu Beznea renesas_i3c_bus_init() performs a number of computations and software cache updates, interleaving them with hardware register writes. While this works today, it makes it harder to minimize the time the controller must remain powered when runtime PM is introduced. Perform all software computations and cache updates first, then update the hardware registers. This prepares for future runtime PM support. Reviewed-by: Frank Li Signed-off-by: Claudiu Beznea --- Changes in v4: - none Changes in v3: - none Changes in v2: - collected tags drivers/i3c/master/renesas-i3c.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/i3c/master/renesas-i3c.c b/drivers/i3c/master/renesas-i3c.c index d5247e841a83..96d4fed32bf9 100644 --- a/drivers/i3c/master/renesas-i3c.c +++ b/drivers/i3c/master/renesas-i3c.c @@ -560,10 +560,6 @@ static int renesas_i3c_bus_init(struct i3c_master_controller *m) if (!i3c->rate) return -EINVAL; - ret = renesas_i3c_reset(i3c); - if (ret) - return ret; - i2c_total_ticks = DIV_ROUND_UP(i3c->rate, bus->scl_rate.i2c); i3c_total_ticks = DIV_ROUND_UP(i3c->rate, bus->scl_rate.i3c); @@ -614,27 +610,31 @@ static int renesas_i3c_bus_init(struct i3c_master_controller *m) STDBR_SBRHO(double_SBR, od_high_ticks) | STDBR_SBRLP(pp_low_ticks) | STDBR_SBRHP(pp_high_ticks); - renesas_writel(i3c->regs, STDBR, i3c->i3c_STDBR); /* Extended Bit Rate setting */ i3c->extbr = EXTBR_EBRLO(od_low_ticks) | EXTBR_EBRHO(od_high_ticks) | EXTBR_EBRLP(pp_low_ticks) | EXTBR_EBRHP(pp_high_ticks); - renesas_writel(i3c->regs, EXTBR, i3c->extbr); - - renesas_writel(i3c->regs, REFCKCTL, REFCKCTL_IREFCKS(cks)); - i3c->refclk_div = cks; - - /* I3C hw init*/ - renesas_i3c_hw_init(i3c); ret = i3c_master_get_free_addr(m, 0); if (ret < 0) return ret; + info.dyn_addr = ret; i3c->dyn_addr = ret; - renesas_writel(i3c->regs, MSDVAD, MSDVAD_MDYAD(ret) | MSDVAD_MDYADV); + i3c->refclk_div = cks; + + ret = renesas_i3c_reset(i3c); + if (ret) + return ret; + + renesas_writel(i3c->regs, STDBR, i3c->i3c_STDBR); + renesas_writel(i3c->regs, EXTBR, i3c->extbr); + renesas_writel(i3c->regs, REFCKCTL, REFCKCTL_IREFCKS(cks)); + renesas_writel(i3c->regs, MSDVAD, MSDVAD_MDYAD(i3c->dyn_addr) | MSDVAD_MDYADV); + + /* I3C hw init*/ + renesas_i3c_hw_init(i3c); - info.dyn_addr = ret; return i3c_master_set_info(&i3c->base, &info); } -- 2.43.0