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[68.48.65.54]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8d30522cbeasm82008446d6.44.2026.06.14.08.56.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Jun 2026 08:56:18 -0700 (PDT) From: Michael Bommarito To: Hans Verkuil , Mauro Carvalho Chehab , Sakari Ailus , Nicolas Dufresne Cc: Laurent Pinchart , Benjamin Gaignard , Detlev Casanova , Ezequiel Garcia , Yunfei Dong , Jonas Karlman , Heiko Stuebner , Kees Cook , linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/6] media: verisilicon: rockchip: bound VPU981 AV1 tile loop and guard divisor Date: Sun, 14 Jun 2026 11:56:06 -0400 Message-ID: <20260614155609.3107600-5-michael.bommarito@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260614155609.3107600-1-michael.bommarito@gmail.com> References: <20260614155609.3107600-1-michael.bommarito@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 7bit rockchip_vpu981_av1_dec_set_tile_info() divides context_update_tile_id by tile_info->tile_cols and writes one descriptor per tile into the tile_info DMA buffer, sized for AV1_MAX_TILES. tile_cols / tile_rows come straight from the bitstream; reject a zero column or row count and bound the grid to AV1_MAX_TILES so the division is safe and the writes stay in the buffer. Fixes: 727a400686a2 ("media: verisilicon: Add Rockchip AV1 decoder") Signed-off-by: Michael Bommarito Assisted-by: Claude:claude-opus-4-8 --- .../verisilicon/rockchip_vpu981_hw_av1_dec.c | 29 +++++++++++++------ 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c index e4e21ad373233..71d2ef72c4402 100644 --- a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c +++ b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c @@ -578,21 +578,32 @@ static void rockchip_vpu981_av1_dec_set_tile_info(struct hantro_ctx *ctx) const struct v4l2_av1_tile_info *tile_info = &ctrls->frame->tile_info; const struct v4l2_ctrl_av1_tile_group_entry *group_entry = ctrls->tile_group_entry; - int context_update_y = - tile_info->context_update_tile_id / tile_info->tile_cols; - int context_update_x = - tile_info->context_update_tile_id % tile_info->tile_cols; - int context_update_tile_id = - context_update_x * tile_info->tile_rows + context_update_y; + unsigned int tile_cols, tile_rows; + int context_update_y, context_update_x, context_update_tile_id; u8 *dst = av1_dec->tile_info.cpu; struct hantro_dev *vpu = ctx->dev; int tile0, tile1; + /* Guard the divisor and bound the grid to the tile_info buffer. */ + tile_cols = tile_info->tile_cols; + tile_rows = tile_info->tile_rows; + if (!tile_cols || !tile_rows) + return; + if (tile_cols * tile_rows > AV1_MAX_TILES) { + tile_cols = min_t(unsigned int, tile_cols, AV1_MAX_TILES); + tile_rows = min_t(unsigned int, tile_rows, + AV1_MAX_TILES / tile_cols); + } + + context_update_y = tile_info->context_update_tile_id / tile_cols; + context_update_x = tile_info->context_update_tile_id % tile_cols; + context_update_tile_id = context_update_x * tile_rows + context_update_y; + memset(dst, 0, av1_dec->tile_info.size); - for (tile0 = 0; tile0 < tile_info->tile_cols; tile0++) { - for (tile1 = 0; tile1 < tile_info->tile_rows; tile1++) { - int tile_id = tile1 * tile_info->tile_cols + tile0; + for (tile0 = 0; tile0 < tile_cols; tile0++) { + for (tile1 = 0; tile1 < tile_rows; tile1++) { + int tile_id = tile1 * tile_cols + tile0; u32 start, end; u32 y0 = tile_info->height_in_sbs_minus_1[tile1] + 1; -- 2.53.0