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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8434b03fd0bsm9968393b3a.50.2026.06.15.05.33.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2026 05:33:12 -0700 (PDT) From: Yingchao Deng Date: Mon, 15 Jun 2026 20:32:30 +0800 Subject: [PATCH v10 2/5] coresight: cti: use __reg_addr() helper for register access Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260615-extended_cti-v10-2-1c1694b6d8ed@oss.qualcomm.com> References: <20260615-extended_cti-v10-0-1c1694b6d8ed@oss.qualcomm.com> In-Reply-To: <20260615-extended_cti-v10-0-1c1694b6d8ed@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, quic_yingdeng@quicinc.com, tingwei.zhang@oss.qualcomm.com, Jinlong Mao , jie.gan@oss.qualcomm.com, Yingchao Deng X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781526782; l=10380; i=yingchao.deng@oss.qualcomm.com; s=20260611; h=from:subject:message-id; bh=wIWFmWKXaUOYZmGF72r5cp1d/iTRLSZHqeXR8U6HAKU=; b=oKoFZXfqqzQ5B4qXkwS1d5b32jbxDCcr+4CRT76qY8Z/leTtADcFEHzQYyrg3F6MrGiGzRT7R MZHH1zEewG5AgAoEp2DMqbVffjU+HyQeW8/lh8ni0K91UjR8UnSTn6E X-Developer-Key: i=yingchao.deng@oss.qualcomm.com; a=ed25519; pk=+y3U2mIt7mf0C+x6qBUD670cd9S2QV+yl5015bUYMgs= X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE1MDEzMiBTYWx0ZWRfX0up1vO5hrl7i 3Phduyf4zT28FF47vSwG6R45RQcWYCvUUeYT7b4E1l7GO0RAMwmaFIwABKJRdVBz0Oleodz+1az aghoJgdAHv0WwutfxDzW07n0fLpton8= X-Authority-Analysis: v=2.4 cv=Zqnd7d7G c=1 sm=1 tr=0 ts=6a2ff10a cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=xqws7DasADjwqOAWw1EA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-GUID: mo0bryC4_fAtUg-csMWeWo22AdncQzki X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE1MDEzMiBTYWx0ZWRfX60KwVJjA/fV0 olZlBA3vr7FqPkhT4Po0MrSvzBRlaj+i19zLs3d90ppGdmuvDYh/Ll742s5NRDxFewiTr4gjFCh DnTLfrEmODywe4AKNItD9rNYMyGu8s4unSj+dOF0AuNsHblCa+bpPMCfhr+dnA1te1d47sS5VQd tUV14kAf0NJr1cKv7Y9VZB60foLNBmiI6hhC5fB7rIcKXVQl9/ED/YiYcKmCoHcPX2anrwiEWPq C43ve+EduNgGEjf5A0kO7QeMaze06KOOPG3S45JaaXdspFvCRio7nK4Eko47yGcn0uC4K6Pc+5l sbZld+4W3iKSBl4eg5Q0oqoqzdqQkN20uh/Y0MFguwUjURaZIipRIwBiZAWjuGPtl5dJxokYN5Y vSRC6OvEftK/l8neblC7eh+VjJdS2UnK91cA4mu4URZbUzNkiCAC3Z/bUc+Wn9aFmZawRT+op0X sMGn2Zt+Bk1o+H6jxdA== X-Proofpoint-ORIG-GUID: mo0bryC4_fAtUg-csMWeWo22AdncQzki X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-15_03,2026-06-15_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 clxscore=1015 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606150132 Introduce a static inline __reg_addr(drvdata, off, index) helper in coresight-cti.h to compute MMIO addresses from a base offset and a per-trigger index, replacing the function-like CTIINEN(n)/CTIOUTEN(n) macros with base offsets and explicit index arithmetic. Add reg_addr and reg_index_addr convenience macros for zero-index and indexed access respectively. Convert cti_read_single_reg() and cti_write_single_reg() to static inline wrappers in coresight-cti.h, and add indexed variants cti_read_single_reg_index() / cti_write_single_reg_index() for callers that need explicit bank selection. Extend cs_off_attribute with a u32 index field and update coresight_cti_reg_show/store to use the attribute's index field directly. Co-developed-by: Jinlong Mao Signed-off-by: Jinlong Mao Signed-off-by: Yingchao Deng drivers/hwtracing/coresight/coresight-cti-core.c | 45 ++++++++++++++--------- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 25 +++++++------ drivers/hwtracing/coresight/coresight-cti.h | 9 +++-- drivers/hwtracing/coresight/coresight-priv.h | 4 +- 4 files changed, 50 insertions(+), 33 deletions(-) --- drivers/hwtracing/coresight/coresight-cti-core.c | 36 +++++------------- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 17 +++++---- drivers/hwtracing/coresight/coresight-cti.h | 46 +++++++++++++++++++++-- drivers/hwtracing/coresight/coresight-priv.h | 4 +- 4 files changed, 64 insertions(+), 39 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c index 572798ab504c..fa758c535ccb 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -55,16 +55,17 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) /* write the CTI trigger registers */ for (i = 0; i < config->nr_trig_max; i++) { - writel_relaxed(config->ctiinen[i], drvdata->base + CTIINEN(i)); + writel_relaxed(config->ctiinen[i], + reg_index_addr(drvdata, CTIINEN, i)); writel_relaxed(config->ctiouten[i], - drvdata->base + CTIOUTEN(i)); + reg_index_addr(drvdata, CTIOUTEN, i)); } /* other regs */ - writel_relaxed(config->ctigate, drvdata->base + CTIGATE); + writel_relaxed(config->ctigate, reg_addr(drvdata, CTIGATE)); if (config->asicctl_impl) - writel_relaxed(config->asicctl, drvdata->base + ASICCTL); - writel_relaxed(config->ctiappset, drvdata->base + CTIAPPSET); + writel_relaxed(config->asicctl, reg_addr(drvdata, ASICCTL)); + writel_relaxed(config->ctiappset, reg_addr(drvdata, CTIAPPSET)); /* re-enable CTI */ writel_relaxed(1, drvdata->base + CTICONTROL); @@ -122,24 +123,6 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) return 0; } -u32 cti_read_single_reg(struct cti_drvdata *drvdata, int offset) -{ - int val; - - CS_UNLOCK(drvdata->base); - val = readl_relaxed(drvdata->base + offset); - CS_LOCK(drvdata->base); - - return val; -} - -void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value) -{ - CS_UNLOCK(drvdata->base); - writel_relaxed(value, drvdata->base + offset); - CS_LOCK(drvdata->base); -} - void cti_write_intack(struct device *dev, u32 ackval) { struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); @@ -333,7 +316,7 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, struct cti_config *config = &drvdata->config; u32 chan_bitmask; u32 reg_value; - int reg_offset; + u32 reg_offset; /* ensure indexes in range */ if ((channel_idx >= config->nr_ctm_channels) || @@ -355,8 +338,7 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, /* update the local register values */ chan_bitmask = BIT(channel_idx); - reg_offset = (direction == CTI_TRIG_IN ? CTIINEN(trigger_idx) : - CTIOUTEN(trigger_idx)); + reg_offset = (direction == CTI_TRIG_IN ? CTIINEN : CTIOUTEN); guard(raw_spinlock_irqsave)(&drvdata->spinlock); @@ -376,7 +358,7 @@ int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, /* write through if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, reg_offset, reg_value); + cti_write_single_reg_index(drvdata, reg_offset, trigger_idx, reg_value); return 0; } diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 2bbfa405cb6b..6165866eaefe 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -171,7 +171,7 @@ static ssize_t coresight_cti_reg_show(struct device *dev, pm_runtime_get_sync(dev->parent); scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) - val = cti_read_single_reg(drvdata, cti_attr->off); + val = cti_read_single_reg_index(drvdata, cti_attr->off, cti_attr->index); pm_runtime_put_sync(dev->parent); return sysfs_emit(buf, "0x%x\n", val); @@ -192,7 +192,7 @@ static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, pm_runtime_get_sync(dev->parent); scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) - cti_write_single_reg(drvdata, cti_attr->off, val); + cti_write_single_reg_index(drvdata, cti_attr->off, cti_attr->index, val); pm_runtime_put_sync(dev->parent); return size; @@ -202,7 +202,8 @@ static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, (&((struct cs_off_attribute[]) { \ { \ __ATTR(name, 0444, coresight_cti_reg_show, NULL), \ - offset \ + offset, \ + 0 \ } \ })[0].attr.attr) @@ -211,7 +212,8 @@ static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, { \ __ATTR(name, 0644, coresight_cti_reg_show, \ coresight_cti_reg_store), \ - offset \ + offset, \ + 0 \ } \ })[0].attr.attr) @@ -219,7 +221,8 @@ static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, (&((struct cs_off_attribute[]) { \ { \ __ATTR(name, 0200, NULL, coresight_cti_reg_store), \ - offset \ + offset, \ + 0 \ } \ })[0].attr.attr) @@ -386,7 +389,7 @@ static ssize_t inen_store(struct device *dev, /* write through if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, CTIINEN(index), val); + cti_write_single_reg_index(drvdata, CTIINEN, index, val); return size; } @@ -427,7 +430,7 @@ static ssize_t outen_store(struct device *dev, /* write through if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, CTIOUTEN(index), val); + cti_write_single_reg_index(drvdata, CTIOUTEN, index, val); return size; } diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracing/coresight/coresight-cti.h index ef079fc18b72..634bdce5cdfd 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -30,8 +30,8 @@ struct fwnode_handle; #define CTIAPPSET 0x014 #define CTIAPPCLEAR 0x018 #define CTIAPPPULSE 0x01C -#define CTIINEN(n) (0x020 + (4 * n)) -#define CTIOUTEN(n) (0x0A0 + (4 * n)) +#define CTIINEN 0x020 +#define CTIOUTEN 0x0A0 #define CTITRIGINSTATUS 0x130 #define CTITRIGOUTSTATUS 0x134 #define CTICHINSTATUS 0x138 @@ -217,8 +217,6 @@ int cti_enable(struct coresight_device *csdev, enum cs_mode mode, int cti_disable(struct coresight_device *csdev, struct coresight_path *path); void cti_write_all_hw_regs(struct cti_drvdata *drvdata); void cti_write_intack(struct device *dev, u32 ackval); -void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 value); -u32 cti_read_single_reg(struct cti_drvdata *drvdata, int offset); int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, enum cti_trig_dir direction, u32 channel_idx, u32 trigger_idx); @@ -231,6 +229,46 @@ struct coresight_platform_data * coresight_cti_get_platform_data(struct device *dev); const char *cti_plat_get_node_name(struct fwnode_handle *fwnode); +static inline void __iomem *__reg_addr(struct cti_drvdata *drvdata, + u32 off, u32 index) +{ + return drvdata->base + off + index * sizeof(u32); +} + +#define reg_addr(drvdata, off) __reg_addr((drvdata), (off), 0) +#define reg_index_addr(drvdata, off, i) __reg_addr((drvdata), (off), (i)) + +static inline u32 cti_read_single_reg_index(struct cti_drvdata *drvdata, + u32 off, u32 index) +{ + u32 val; + + CS_UNLOCK(drvdata->base); + val = readl_relaxed(reg_index_addr(drvdata, off, index)); + CS_LOCK(drvdata->base); + + return val; +} + +static inline u32 cti_read_single_reg(struct cti_drvdata *drvdata, u32 off) +{ + return cti_read_single_reg_index(drvdata, off, 0); +} + +static inline void cti_write_single_reg_index(struct cti_drvdata *drvdata, + u32 off, u32 index, u32 value) +{ + CS_UNLOCK(drvdata->base); + writel_relaxed(value, reg_index_addr(drvdata, off, index)); + CS_LOCK(drvdata->base); +} + +static inline void cti_write_single_reg(struct cti_drvdata *drvdata, + u32 off, u32 value) +{ + cti_write_single_reg_index(drvdata, off, 0, value); +} + /* Check if a cti device is enabled */ static inline bool cti_is_active(struct cti_config *cfg) { diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index dddac946659f..cb4736324c04 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -58,6 +58,7 @@ struct cs_pair_attribute { struct cs_off_attribute { struct device_attribute attr; u32 off; + u32 index; }; ssize_t coresight_simple_show32(struct device *_dev, struct device_attribute *attr, char *buf); @@ -67,7 +68,8 @@ ssize_t coresight_simple_show_pair(struct device *_dev, struct device_attribute (&((struct cs_off_attribute[]) { \ { \ __ATTR(name, 0444, coresight_simple_show32, NULL), \ - offset \ + offset, \ + 0 \ } \ })[0].attr.attr) -- 2.43.0