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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8434b03fd0bsm9968393b3a.50.2026.06.15.05.33.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2026 05:33:19 -0700 (PDT) From: Yingchao Deng Date: Mon, 15 Jun 2026 20:32:32 +0800 Subject: [PATCH v10 4/5] coresight: cti: expose banked sysfs registers for Qualcomm extended CTI Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260615-extended_cti-v10-4-1c1694b6d8ed@oss.qualcomm.com> References: <20260615-extended_cti-v10-0-1c1694b6d8ed@oss.qualcomm.com> In-Reply-To: <20260615-extended_cti-v10-0-1c1694b6d8ed@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, quic_yingdeng@quicinc.com, tingwei.zhang@oss.qualcomm.com, Jinlong Mao , jie.gan@oss.qualcomm.com, Yingchao Deng X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781526782; l=5618; i=yingchao.deng@oss.qualcomm.com; s=20260611; h=from:subject:message-id; bh=nLJJ2LG0916NbMbQC/CB2id4JlgiNIupcL84YiH1LSI=; b=6mqmr4mIJpAqOe8iXiZqcp1T2fvrZ54s8SytoqqlhFhB5g/CboVG2Byq6U3yCs/mg2C0SQ2CY +beqXV9dsbgAGvuc7m+JPrn98/qQ+9y2xSYmZBE3wbiXwNXFWQvTaTs X-Developer-Key: i=yingchao.deng@oss.qualcomm.com; a=ed25519; pk=+y3U2mIt7mf0C+x6qBUD670cd9S2QV+yl5015bUYMgs= X-Proofpoint-GUID: 53iOm4DZsE5XdxhC4cK0wAGq7sYsKprt X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE1MDEzMiBTYWx0ZWRfX1CMQ3sad3+Cm seZz9+eTh/LMgDtOUAONSMW1WCxqqH5G4JFEVTmDQ6D+q1i9rCNqr8A3rSf4pwRNZu9vJWDOUsY wy4OYFd78N3pqhPwTaQdX40GzCUvNVM= X-Authority-Analysis: v=2.4 cv=QrJuG1yd c=1 sm=1 tr=0 ts=6a2ff111 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=7CQSdrXTAAAA:8 a=EUspDBNiAAAA:8 a=yoa6GI8vE20v00mW0vsA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-Proofpoint-ORIG-GUID: 53iOm4DZsE5XdxhC4cK0wAGq7sYsKprt X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE1MDEzMiBTYWx0ZWRfX8jUme27MOYn9 rugrWUD2DsDAtFGbwA+ZFlRG02bqNj0thSprNENhfbAzNtrFQANDf8GFHqXJ+Yr64cPg98xtxeP 7RcVmyl52OIQCQTE0OS+dPPrGJuEQkMBh/uCPX2cfD44kf0MeRHNb3kpN6ThcPAuJ9KssABslqM XDOAxBtlEoO0PXOONGhKPqftuGb/H2IaLgM25p5mNfrA8jvn/SsT48lY0R/9ASuE/t6a6chXCgg 8XzRCrHzXz6rKG+XRYFmxf7Ltkw+WeAJEJlCxg+h/ZGe3tr2CCS1Nql8cjQQ12mKmP62qiNKvCt VgrP4ZkqC3dIN7lIfXFMhKzMxdedG4uMdMjV5NRL020fEAN+GkmrmxWvgD1q5vHqFkfUcmuPLVW VRkcexr3cc5L7tSUXS6x8cUKZQ7flKUIEPqfqMrch5+C2jkdaisss3/UYKAcgo0zej+Y5fb/YWI eM0nxbBvTyWuKnTxSIg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-15_03,2026-06-15_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 suspectscore=0 phishscore=0 spamscore=0 impostorscore=0 malwarescore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606150132 Qualcomm extended CTI implements banked trigger status and integration registers, where each bank covers 32 triggers. Multiple instances of these registers are required to expose the full trigger space. Add coresight_cti_reg_index(), coresight_cti_reg_rw_index(), and coresight_cti_reg_wo_index() macros that carry the bank index in the cs_off_attribute.index field, keeping the base offset and index separate rather than encoding them together. Add static sysfs entries for the banked CTI registers and control their visibility based on the underlying hardware configuration. Visibility is determined by comparing the attribute's index against the number of banks implied by nr_trig_max (32 triggers per bank). Registers beyond the hardware capacity are hidden, preserving the existing ABI on standard ARM CTIs while exposing the full register set on Qualcomm CTIs. Reviewed-by: Leo Yan Signed-off-by: Yingchao Deng --- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 58 +++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 6165866eaefe..175f20d69232 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -207,6 +207,15 @@ static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, } \ })[0].attr.attr) +#define coresight_cti_reg_index(name, offset, idx) \ + (&((struct cs_off_attribute[]) { \ + { \ + __ATTR(name, 0444, coresight_cti_reg_show, NULL), \ + offset, \ + idx \ + } \ + })[0].attr.attr) + #define coresight_cti_reg_rw(name, offset) \ (&((struct cs_off_attribute[]) { \ { \ @@ -217,6 +226,16 @@ static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, } \ })[0].attr.attr) +#define coresight_cti_reg_rw_index(name, offset, idx) \ + (&((struct cs_off_attribute[]) { \ + { \ + __ATTR(name, 0644, coresight_cti_reg_show, \ + coresight_cti_reg_store), \ + offset, \ + idx \ + } \ + })[0].attr.attr) + #define coresight_cti_reg_wo(name, offset) \ (&((struct cs_off_attribute[]) { \ { \ @@ -226,6 +245,15 @@ static __maybe_unused ssize_t coresight_cti_reg_store(struct device *dev, } \ })[0].attr.attr) +#define coresight_cti_reg_wo_index(name, offset, idx) \ + (&((struct cs_off_attribute[]) { \ + { \ + __ATTR(name, 0200, NULL, coresight_cti_reg_store), \ + offset, \ + idx \ + } \ + })[0].attr.attr) + /* coresight management registers */ static struct attribute *coresight_cti_mgmt_attrs[] = { coresight_cti_reg(devaff0, CTIDEVAFF0), @@ -515,18 +543,36 @@ static struct attribute *coresight_cti_regs_attrs[] = { &dev_attr_appclear.attr, &dev_attr_apppulse.attr, coresight_cti_reg(triginstatus, CTITRIGINSTATUS), + coresight_cti_reg_index(triginstatus1, CTITRIGINSTATUS, 1), + coresight_cti_reg_index(triginstatus2, CTITRIGINSTATUS, 2), + coresight_cti_reg_index(triginstatus3, CTITRIGINSTATUS, 3), coresight_cti_reg(trigoutstatus, CTITRIGOUTSTATUS), + coresight_cti_reg_index(trigoutstatus1, CTITRIGOUTSTATUS, 1), + coresight_cti_reg_index(trigoutstatus2, CTITRIGOUTSTATUS, 2), + coresight_cti_reg_index(trigoutstatus3, CTITRIGOUTSTATUS, 3), coresight_cti_reg(chinstatus, CTICHINSTATUS), coresight_cti_reg(choutstatus, CTICHOUTSTATUS), #ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS coresight_cti_reg_rw(itctrl, CORESIGHT_ITCTRL), coresight_cti_reg(ittrigin, ITTRIGIN), + coresight_cti_reg_index(ittrigin1, ITTRIGIN, 1), + coresight_cti_reg_index(ittrigin2, ITTRIGIN, 2), + coresight_cti_reg_index(ittrigin3, ITTRIGIN, 3), coresight_cti_reg(itchin, ITCHIN), coresight_cti_reg_rw(ittrigout, ITTRIGOUT), + coresight_cti_reg_rw_index(ittrigout1, ITTRIGOUT, 1), + coresight_cti_reg_rw_index(ittrigout2, ITTRIGOUT, 2), + coresight_cti_reg_rw_index(ittrigout3, ITTRIGOUT, 3), coresight_cti_reg_rw(itchout, ITCHOUT), coresight_cti_reg(itchoutack, ITCHOUTACK), coresight_cti_reg(ittrigoutack, ITTRIGOUTACK), + coresight_cti_reg_index(ittrigoutack1, ITTRIGOUTACK, 1), + coresight_cti_reg_index(ittrigoutack2, ITTRIGOUTACK, 2), + coresight_cti_reg_index(ittrigoutack3, ITTRIGOUTACK, 3), coresight_cti_reg_wo(ittriginack, ITTRIGINACK), + coresight_cti_reg_wo_index(ittriginack1, ITTRIGINACK, 1), + coresight_cti_reg_wo_index(ittriginack2, ITTRIGINACK, 2), + coresight_cti_reg_wo_index(ittriginack3, ITTRIGINACK, 3), coresight_cti_reg_wo(itchinack, ITCHINACK), #endif NULL, @@ -537,10 +583,22 @@ static umode_t coresight_cti_regs_is_visible(struct kobject *kobj, { struct device *dev = kobj_to_dev(kobj); struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct device_attribute *dev_attr; + struct cs_off_attribute *cti_attr; + int max_bank; if (attr == &dev_attr_asicctl.attr && !drvdata->config.asicctl_impl) return 0; + dev_attr = container_of(attr, struct device_attribute, attr); + if (dev_attr->show == coresight_cti_reg_show || + dev_attr->store == coresight_cti_reg_store) { + cti_attr = container_of(dev_attr, struct cs_off_attribute, attr); + max_bank = DIV_ROUND_UP(drvdata->config.nr_trig_max, 32); + if (cti_attr->index >= max_bank) + return 0; + } + return attr->mode; } -- 2.43.0