drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:1122:38: sparse: sparse: cast from restricted __le64

[kernel test robot <lkp@intel.com>]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head:   8cd9520d35a6c38db6567e97dd93b1f11f185dc6
commit: 7cad800485956a263318930613f8f4a084af8c70 iommu/arm-smmu-v3: Mark EATS_TRANS safe when computing the update sequence
date:   5 months ago
config: arm64-randconfig-r123-20260614 (https://download.01.org/0day-ci/archive/20260615/202606151017.QU0evpH9-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 13.4.0
sparse: v0.6.5-rc1
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260615/202606151017.QU0evpH9-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Fixes: 7cad80048595 ("iommu/arm-smmu-v3: Mark EATS_TRANS safe when computing the update sequence")
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202606151017.QU0evpH9-lkp@intel.com/

sparse warnings: (new ones prefixed by >>)
   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:1101:17: sparse: sparse: incorrect type in initializer (different base types) @@     expected restricted __le64 const [usertype] eats_s1chk @@     got unsigned long long @@
   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:1101:17: sparse:     expected restricted __le64 const [usertype] eats_s1chk
   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:1101:17: sparse:     got unsigned long long
   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:1103:17: sparse: sparse: incorrect type in initializer (different base types) @@     expected restricted __le64 const [usertype] eats_trans @@     got unsigned long long @@
   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:1103:17: sparse:     expected restricted __le64 const [usertype] eats_trans
   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:1103:17: sparse:     got unsigned long long
>> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:1122:38: sparse: sparse: cast from restricted __le64
   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c:1124:33: sparse: sparse: cast from restricted __le64
   drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c: note: in included file (through arch/arm64/include/asm/atomic.h, include/linux/atomic.h, include/asm-generic/bitops/atomic.h, ...):
   arch/arm64/include/asm/cmpxchg.h:168:1: sparse: sparse: cast truncates bits from constant value (ffffffff80000000 becomes 0)
   arch/arm64/include/asm/cmpxchg.h:168:1: sparse: sparse: cast truncates bits from constant value (ffffffff80000000 becomes 0)

vim +1122 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

  1095	
  1096	VISIBLE_IF_KUNIT
  1097	void arm_smmu_get_ste_update_safe(const __le64 *cur, const __le64 *target,
  1098					  __le64 *safe_bits)
  1099	{
  1100		const __le64 eats_s1chk =
  1101			FIELD_PREP(STRTAB_STE_1_EATS, STRTAB_STE_1_EATS_S1CHK);
  1102		const __le64 eats_trans =
  1103			FIELD_PREP(STRTAB_STE_1_EATS, STRTAB_STE_1_EATS_TRANS);
  1104	
  1105		/*
  1106		 * When an STE changes EATS_TRANS, the sequencing code in the attach
  1107		 * logic already will have the PCI cap for ATS disabled. Thus at this
  1108		 * moment we can expect that the device will not generate ATS queries
  1109		 * and so we don't care about the sequencing of EATS. The purpose of
  1110		 * EATS_TRANS is to protect the system from hostile untrusted devices
  1111		 * that issue ATS when the PCI config space is disabled. However, if
  1112		 * EATS_TRANS is being changed, then we must have already trusted the
  1113		 * device as the EATS_TRANS security block is being disabled.
  1114		 *
  1115		 *  Note: now the EATS_TRANS update is moved to the first entry_set().
  1116		 *  Changing S2S and EATS might transiently result in S2S=1 and EATS=1
  1117		 *  which is a bad STE (see "5.2 Stream Table Entry"). In such a case,
  1118		 *  we can't do a hitless update. Also, it should not be added to the
  1119		 *  safe bits with STRTAB_STE_1_EATS_S1CHK, because EATS=0b11 would be
  1120		 *  effectively an errant 0b00 configuration.
  1121		 */
> 1122		if (!((cur[1] | target[1]) & cpu_to_le64(eats_s1chk)) &&
  1123		    !((cur[2] | target[2]) & cpu_to_le64(STRTAB_STE_2_S2S)))
  1124			safe_bits[1] |= cpu_to_le64(eats_trans);
  1125	
  1126		/*
  1127		 * MEV does not meaningfully impact the operation of the HW, it only
  1128		 * changes how many fault events are generated, thus we can relax it
  1129		 * when computing the ordering. The spec notes the device can act like
  1130		 * MEV=1 anyhow:
  1131		 *
  1132		 *  Note: Software must expect, and be able to deal with, coalesced
  1133		 *  fault records even when MEV == 0.
  1134		 */
  1135		safe_bits[1] |= cpu_to_le64(STRTAB_STE_1_MEV);
  1136	}
  1137	EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_update_safe);
  1138	

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