From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from naesa05.arrow.com (naesa05.arrow.com [216.150.161.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEE333E866C; Mon, 15 Jun 2026 12:21:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=216.150.161.26 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781526090; cv=none; b=O0Xf7166qW8/FBw2hK3pExWIT1gK4Inii44Zn6PoN8igt/RNX8afAJGZ8UDtZwo3uHecODQi9YAuh2GA6hmmGv1+dwags6sVxo8z2kbP84yYJ00MvnZIsXU+EnKwNEzmdPTF0S/1pbc5Jx9XJkszuTNyXuOpvGSoJ14ZNO2/UF4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781526090; c=relaxed/simple; bh=E4UJjPbIbx/AMRxoHb0usfCVZCCwtCrFuUv99B+UnfI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jm0gwRCMWiaf8KNIXV4SMsl4u1m8/hQyEPHSh6NyW7UzqCK1E0phKXBTsxpGW6PeDGbObVXcpuDSRk/oCbquFJGTFKK1O7OM7wIAe543XUFE2fhV1L4i2nQnRroStgTBhdosyOCT4KufAHdBu4ZPZMvCy8Lsl/I4/UIF01swoek= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=einfochips.com; spf=pass smtp.mailfrom=einfochips.com; dkim=pass (2048-bit key) header.d=einfochips.com header.i=@einfochips.com header.b=WGlO0tRm; arc=none smtp.client-ip=216.150.161.26 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=einfochips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=einfochips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=einfochips.com header.i=@einfochips.com header.b="WGlO0tRm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=einfochips.com; i=@einfochips.com; l=1890; q=dns/txt; s=NAESA-Selector1; t=1781526089; x=1813062089; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vvvQffFpjs/VksFWNOIERELN6UIGdOwIgArUo+fkTPo=; b=WGlO0tRmdRiXwZI7NTLYDgd+hEal0MEJrpx3p5s+Lsx8nyStxzmSUdpP mml5Ih2HTh0lVDXcDvlxlJFca4Y9V2ST6QC96eDXrOEz6pfEbAk/ypuIb TzDdeoeNDJHOXZRkWQ0Iito+4wilVvDuZ7QCSeP0Huf+jm07GPm12a226 Sp6olf44ZdChlZ4UjpKQaahe7u9q4vcbGtXvcpWGa0E6I6sI21dA3K3UP ta6G52HPlmUnqPLb8W5VVNIf/a3qv0kbVtnVMZodvBz3pKoZ12Zf88l33 FUhTlC25R9bI1HJa/8S5eahGYIvCCT1+ONN/PWMeOlQQKJE5AIBo73MMw A==; X-CSE-ConnectionGUID: 0UyMlXg/QVGVO5QCy9Q4kQ== X-CSE-MsgGUID: ecQ1NBbKTDuOl2WWoQ/fUA== X-IronPort-AV: E=Sophos;i="6.24,206,1774332000"; d="scan'208";a="55984201" Received: from unknown (HELO eicahmirelay01.einfochips.com) ([10.100.49.50]) by naesa05out.arrow.com with ESMTP; 15 Jun 2026 06:20:20 -0600 Received: from AHMCPU1888.ap.corp.arrow.com ([172.25.5.100]) by eicahmirelay01.einfochips.com with Microsoft SMTPSVC(10.0.20348.1); Mon, 15 Jun 2026 17:50:16 +0530 From: Pinkesh Vaghela To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Min Lin Cc: Yulin Lu , Samuel Holland , Darshan Prajapati , Pinkesh Vaghela , Pritesh Patel Subject: [PATCH 2/7] riscv: dts: eswin: add clock generator for EIC7700 SoC Date: Mon, 15 Jun 2026 17:50:11 +0530 Message-Id: <20260615122016.1110206-3-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260615122016.1110206-1-pinkesh.vaghela@einfochips.com> References: <20260615122016.1110206-1-pinkesh.vaghela@einfochips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 15 Jun 2026 12:20:16.0878 (UTC) FILETIME=[532F78E0:01DCFCC1] From: Pritesh Patel Add clock generator node for EIC7700 SoC. HiFive Premier P550 boards have 24MHz crystal oscillator to provide the input clock. Signed-off-by: Pritesh Patel Signed-off-by: Pinkesh Vaghela --- .../boot/dts/eswin/eic7700-hifive-premier-p550.dts | 5 +++++ arch/riscv/boot/dts/eswin/eic7700.dtsi | 13 +++++++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts index 131ed1fc6b2e..1fb92f0e7c55 100644 --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts @@ -20,6 +20,11 @@ chosen { }; }; +&xtal { + clock-frequency = <24000000>; + clock-output-names = "xtal24m"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi index 430a210f01e6..a7ebb1115958 100644 --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi @@ -4,6 +4,7 @@ */ /dts-v1/; +#include #include / { @@ -203,6 +204,11 @@ pmu { <0x00000000 0x0000000f 0xfffffffc 0x000000ff 0x00000078>; }; + xtal: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; ranges; @@ -343,6 +349,13 @@ gpioD: gpio-port@3 { }; }; + clk: clock-controller@51828000 { + compatible = "eswin,eic7700-clock"; + reg = <0x0 0x51828000 0x0 0x300>; + clocks = <&xtal>; + #clock-cells = <1>; + }; + reset: reset-controller@51828300 { compatible = "eswin,eic7700-reset"; reg = <0x0 0x51828300 0x0 0x200>; -- 2.34.1