From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from naesa05.arrow.com (naesa05.arrow.com [216.150.161.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E7C8353EC0; Mon, 15 Jun 2026 12:20:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=216.150.161.26 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781526029; cv=none; b=Y2k02sd3MUebY2tGfFXjTGgGjyfGomO9EhwCdHteJl4sfaZhBjZwW3blLxVnSlGDRQ1rwItWhCCCg8q0XgQDtWovQVCRja+xJzNGFuaXXARAubjOAy8Fjo34QLqRbl2nQ/qADPVCKaKmcLpH8htDl5k/DlnuTGSd/bDZgBaJxtA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781526029; c=relaxed/simple; bh=0qUl1wRzhO6PayJghujEdOaMAsFcOeaTkKomMhlfpEg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=q4YT941ZEh681cWi+1I/fczA1Ndg0VAWRneRfxD/8InsEXTH6qllu29+bLZmNL8XqeyPi2sjH1Ldzsut8GSGpUD+dsxpPDaTxRQILGVKKMQcMxto0C+cb/I8mvnXBOGnsFzpfRO6D756zywDEBBI/o+xwEiTrt5EOpmrMhtESjY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=einfochips.com; spf=pass smtp.mailfrom=einfochips.com; dkim=pass (2048-bit key) header.d=einfochips.com header.i=@einfochips.com header.b=RX5vMNqf; arc=none smtp.client-ip=216.150.161.26 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=einfochips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=einfochips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=einfochips.com header.i=@einfochips.com header.b="RX5vMNqf" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=einfochips.com; i=@einfochips.com; l=6367; q=dns/txt; s=NAESA-Selector1; t=1781526027; x=1813062027; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=h8KdvRyvHHTj2syROXivFVLOUiLh0AiF2uqplzqCgi0=; b=RX5vMNqfZJFmDyt3UAns0e3nxLvRLCfNlGL5XF1BnOMuQLwHdWpd5B9w va0cp3Jn4+c9aUSkCrDvmEYqqlL6UPYPr871LosHO26ynmwqbYa8dQZzq bXdsVb4+sMk3L6jwo5NcW0moMZA3juHFx7ds3ntUlXKZtgFLAEbbg2hJ0 Fk+S/pzsU+l19UTwY2diHfWv8CeBOoaPZngkKfblG3RWQ44tf5bTBlu+I Fhc2wN4ZoagXhh5fAMSxA+LDICVl33goKgSTuxK/GvNOjjfIm9aj6OnOB tEOblyU0sXVEfvi1bzLQVmmJw1cc7QCF+PehZMzxVQUeruoh9CcTCcxB5 w==; X-CSE-ConnectionGUID: uKFetQmLR6CBPDx+ZiVGPg== X-CSE-MsgGUID: VbbYT8EVSnqT/Gu/QZ+11w== X-IronPort-AV: E=Sophos;i="6.24,206,1774332000"; d="scan'208";a="55984210" Received: from unknown (HELO eicahmirelay01.einfochips.com) ([10.100.49.50]) by naesa05out.arrow.com with ESMTP; 15 Jun 2026 06:20:26 -0600 Received: from AHMCPU1888.ap.corp.arrow.com ([172.25.5.100]) by eicahmirelay01.einfochips.com with Microsoft SMTPSVC(10.0.20348.1); Mon, 15 Jun 2026 17:50:17 +0530 From: Pinkesh Vaghela To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Min Lin Cc: Yulin Lu , Samuel Holland , Darshan Prajapati , Pinkesh Vaghela , Pritesh Patel Subject: [PATCH 6/7] riscv: dts: eswin: add I2C controller support Date: Mon, 15 Jun 2026 17:50:15 +0530 Message-Id: <20260615122016.1110206-7-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260615122016.1110206-1-pinkesh.vaghela@einfochips.com> References: <20260615122016.1110206-1-pinkesh.vaghela@einfochips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 15 Jun 2026 12:20:17.0052 (UTC) FILETIME=[534A05C0:01DCFCC1] From: Pritesh Patel Add I2C nodes for EIC7700 SoC. Also add nodes for corresponding slave devices in dts file and enable them for HiFive Premier P550 board Signed-off-by: Pritesh Patel Signed-off-by: Pinkesh Vaghela --- .../dts/eswin/eic7700-hifive-premier-p550.dts | 52 ++++++ arch/riscv/boot/dts/eswin/eic7700.dtsi | 156 ++++++++++++++++++ 2 files changed, 208 insertions(+) diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts index e7bb96e14958..0f0c98474c62 100644 --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts @@ -130,6 +130,58 @@ &gpio111_pins { input-disable; }; +&aon_i2c0 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; +}; + +&aon_i2c1 { + status = "okay"; + + pac1934@10 { + compatible = "microchip,pac1934"; + reg = <0x10>; + #address-cells = <1>; + #size-cells = <0>; + + channel@1 { + reg = <0x1>; + shunt-resistor-micro-ohms = <1000>; + label = "VDD_SOM"; + }; + + channel@2 { + reg = <0x2>; + shunt-resistor-micro-ohms = <1000>; + label = "VDD_SOC"; + }; + + channel@3 { + reg = <0x3>; + shunt-resistor-micro-ohms = <1000>; + label = "VDD_CPU"; + }; + + channel@4 { + reg = <0x4>; + shunt-resistor-micro-ohms = <1000>; + label = "VDD_LPDDR"; + }; + }; + + ina226@44 { + compatible = "ti,ina226"; + reg = <0x44>; + #io-channel-cells = <1>; + label = "sys_power"; + shunt-resistor = <1000>; + }; +}; + &pinctrl { vrgmii-supply = <&vcc_1v8>; }; diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi index f8caf39616b2..28706431b2c0 100644 --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi @@ -315,6 +315,162 @@ uart4: serial@50940000 { status = "disabled"; }; + i2c0: i2c@50950000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x50950000 0x0 0x8000>; + interrupts = <105>; + clocks = <&clk EIC7700_CLK_GATE_LSP_I2C0_PCLK>; + clock-names = "ref"; + clock-frequency = <100000>; + resets = <&reset EIC7700_RESET_I2C0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@50960000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x50960000 0x0 0x8000>; + interrupts = <106>; + clocks = <&clk EIC7700_CLK_GATE_LSP_I2C1_PCLK>; + clock-names = "ref"; + clock-frequency = <100000>; + resets = <&reset EIC7700_RESET_I2C1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@50970000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x50970000 0x0 0x8000>; + interrupts = <107>; + clocks = <&clk EIC7700_CLK_GATE_LSP_I2C2_PCLK>; + clock-names = "ref"; + clock-frequency = <100000>; + resets = <&reset EIC7700_RESET_I2C2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@50980000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x50980000 0x0 0x8000>; + interrupts = <108>; + clocks = <&clk EIC7700_CLK_GATE_LSP_I2C3_PCLK>; + clock-names = "ref"; + clock-frequency = <100000>; + resets = <&reset EIC7700_RESET_I2C3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@50990000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x50990000 0x0 0x8000>; + interrupts = <109>; + clocks = <&clk EIC7700_CLK_GATE_LSP_I2C4_PCLK>; + clock-names = "ref"; + clock-frequency = <100000>; + resets = <&reset EIC7700_RESET_I2C4>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@509a0000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x509a0000 0x0 0x8000>; + interrupts = <110>; + clocks = <&clk EIC7700_CLK_GATE_LSP_I2C5_PCLK>; + clock-names = "ref"; + clock-frequency = <100000>; + resets = <&reset EIC7700_RESET_I2C5>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@509b0000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x509b0000 0x0 0x8000>; + interrupts = <111>; + clocks = <&clk EIC7700_CLK_GATE_LSP_I2C6_PCLK>; + clock-names = "ref"; + clock-frequency = <100000>; + resets = <&reset EIC7700_RESET_I2C6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@509c0000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x509c0000 0x0 0x8000>; + interrupts = <112>; + clocks = <&clk EIC7700_CLK_GATE_LSP_I2C7_PCLK>; + clock-names = "ref"; + clock-frequency = <100000>; + resets = <&reset EIC7700_RESET_I2C7>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@509d0000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x509d0000 0x0 0x8000>; + interrupts = <113>; + clocks = <&clk EIC7700_CLK_GATE_LSP_I2C8_PCLK>; + clock-names = "ref"; + clock-frequency = <100000>; + resets = <&reset EIC7700_RESET_I2C8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@509e0000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x509e0000 0x0 0x8000>; + interrupts = <114>; + clocks = <&clk EIC7700_CLK_GATE_LSP_I2C9_PCLK>; + clock-names = "ref"; + clock-frequency = <100000>; + resets = <&reset EIC7700_RESET_I2C9>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + aon_i2c0: i2c@51830000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x51830000 0x0 0x8000>; + interrupts = <290>; + clocks = <&clk EIC7700_CLK_GATE_AON_I2C0_PCLK>; + clock-names = "ref"; + clock-frequency = <100000>; + resets = <&reset EIC7700_RESET_ANO0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + aon_i2c1: i2c@51838000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x51838000 0x0 0x8000>; + interrupts = <291>; + clocks = <&clk EIC7700_CLK_GATE_AON_I2C1_PCLK>; + clock-names = "ref"; + clock-frequency = <100000>; + resets = <&reset EIC7700_RESET_ANO1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gpio@51600000 { compatible = "snps,dw-apb-gpio"; reg = <0x0 0x51600000 0x0 0x80>; -- 2.34.1