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X-CSE-ConnectionGUID: oJteXpTOSuWWGk0jdC0lYA== X-CSE-MsgGUID: +azUmjJkTMaxi0ikW93QVQ== X-IronPort-AV: E=Sophos;i="6.24,206,1774332000"; d="scan'208";a="55984212" Received: from unknown (HELO eicahmirelay01.einfochips.com) ([10.100.49.50]) by naesa05out.arrow.com with ESMTP; 15 Jun 2026 06:20:27 -0600 Received: from AHMCPU1888.ap.corp.arrow.com ([172.25.5.100]) by eicahmirelay01.einfochips.com with Microsoft SMTPSVC(10.0.20348.1); Mon, 15 Jun 2026 17:50:17 +0530 From: Pinkesh Vaghela To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Min Lin Cc: Yulin Lu , Samuel Holland , Darshan Prajapati , Pinkesh Vaghela , Pritesh Patel Subject: [PATCH 7/7] riscv: dts: eswin: add watchdog support Date: Mon, 15 Jun 2026 17:50:16 +0530 Message-Id: <20260615122016.1110206-8-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260615122016.1110206-1-pinkesh.vaghela@einfochips.com> References: <20260615122016.1110206-1-pinkesh.vaghela@einfochips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 15 Jun 2026 12:20:17.0084 (UTC) FILETIME=[534EE7C0:01DCFCC1] From: Pritesh Patel Add watchdog node for ESWIN EIC7700 SoC and enable them for HiFive Premier P550 board Signed-off-by: Pritesh Patel Signed-off-by: Pinkesh Vaghela --- .../dts/eswin/eic7700-hifive-premier-p550.dts | 16 ++++++++ arch/riscv/boot/dts/eswin/eic7700.dtsi | 40 +++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts index 0f0c98474c62..a188a5e1d526 100644 --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts @@ -193,3 +193,19 @@ &uart0 { &uart2 { status = "okay"; }; + +&wdt0 { + status = "okay"; +}; + +&wdt1 { + status = "okay"; +}; + +&wdt2 { + status = "okay"; +}; + +&wdt3 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi index 28706431b2c0..a59a9932be0b 100644 --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi @@ -265,6 +265,46 @@ hsp_sp_csr: hsp-sp-top-csr@50440000 { }; }; + wdt0: watchdog@50800000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0x50800000 0x0 0x4000>; + interrupts = <87>; + clocks =<&clk EIC7700_CLK_GATE_LSP_WDT0_PCLK>; + clock-names = "tclk"; + resets = <&reset EIC7700_RESET_WDT0>; + status = "disabled"; + }; + + wdt1: watchdog@50804000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0x50804000 0x0 0x4000>; + interrupts = <88>; + clocks =<&clk EIC7700_CLK_GATE_LSP_WDT1_PCLK>; + clock-names = "tclk"; + resets = <&reset EIC7700_RESET_WDT1>; + status = "disabled"; + }; + + wdt2: watchdog@50808000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0x50808000 0x0 0x4000>; + interrupts = <89>; + clocks =<&clk EIC7700_CLK_GATE_LSP_WDT2_PCLK>; + clock-names = "tclk"; + resets = <&reset EIC7700_RESET_WDT2>; + status = "disabled"; + }; + + wdt3: watchdog@5080c000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0x5080c000 0x0 0x4000>; + interrupts = <90>; + clocks =<&clk EIC7700_CLK_GATE_LSP_WDT3_PCLK>; + clock-names = "tclk"; + resets = <&reset EIC7700_RESET_WDT3>; + status = "disabled"; + }; + uart0: serial@50900000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x50900000 0x0 0x10000>; -- 2.34.1