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Tue, 16 Jun 2026 02:26:04 -0700 (PDT) Received: from hu-mkshah-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c42f2e586bsm130042025ad.12.2026.06.16.02.25.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 02:26:03 -0700 (PDT) From: Maulik Shah Subject: [PATCH v3 0/8] x1e80100: Enable PDC wake GPIOs and deepest idle state Date: Tue, 16 Jun 2026 14:55:50 +0530 Message-Id: <20260616-hamoa_pdc_v3-v3-0-4d8e1504ea75@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-B4-Tracking: v=1; b=H4sIAJ8WMWoC/y2NSwqEMBAFryK9NhCjhsGriEjstGML/hIVQby7m dFlQb16J3hyTB6K6ARHO3uexgBpHAF2ZvySYBsYlFRaapmLzgyTqWeL9Z4KbU2DnyyXKkEIk9l Ry8c/V1YP+63pCddf4zUcLVv4WV/tum45NK7FhQAAAA== X-Change-ID: 20260605-hamoa_pdc_v3-6dabc845021c To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Linus Walleij Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, Sneh Mankad , Maulik Shah , Stephan Gerhold X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781601959; l=7964; i=maulik.shah@oss.qualcomm.com; s=20240109; h=from:subject:message-id; bh=oKCA3rXYCYVsu2qwFtdFelHjE9P2vs0ADX+IZRTIOVw=; b=QqpBGBOHRz3NrRFvEbN6/R8EinvO/+gWnTMmgVhVCZBWeGzpU0ChS6UCwJbnpXsyCqeZMfN36 C0aDJTWDnkPBvcdcuAiqzGi/Q0KjGSefnuLR9vqVYcXv0rlAVj5SsU5 X-Developer-Key: i=maulik.shah@oss.qualcomm.com; a=ed25519; pk=bd9h5FIIliUddIk8p3BlQWBlzKEQ/YW5V+fe759hTWQ= X-Proofpoint-GUID: tc9Xsfq5Ub0QJZoSrxIXLC_yEPlhadB8 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE2MDA5NCBTYWx0ZWRfXwlQlus1wA6Al RTtaLDoWxqLA0+l+Cch9LS7Fdmkv2Lnld5De1TEIToOnnFJe0Ltzjb7UPWp1m+L8Hkej5bIXSKR tBm/5AOV4mk+GGFZtPvlsimy9lWtKLI= X-Authority-Analysis: v=2.4 cv=WNdPmHsR c=1 sm=1 tr=0 ts=6a3116ad cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=bC-a23v3AAAA:8 a=aMSERw3ZVSxg4zp0N1wA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=FO4_E8m0qiDe52t0p3_H:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE2MDA5NCBTYWx0ZWRfX8cd2KkYZOA+V +kaRr7VcCcNQveso61UWubf+2EtLBwX5VROXOG79i/aF46Td6jUMP/wXe24r1NNt42hYyl9iB/V Jn2mDyEDbqZTR9UN7zuw5TnK9a4G0ImQUsh7y8g+KdpI5IP9kdA5kzr3HzAcPvOxeIkXl0nET+n JWart/xKPGRMcSm5mASMjjRWecoro317Btbn3Rrkp3q/deUYIjNZ/1UWHNI6Z7cKFRHn8M/qqo9 EnEu4M77awFT2Z2OvOVcSWTN0XR8xtg8lbK07vE4JXfRGga/euCesI60huoe70He1LNfY2j1nQ0 EPfOuHJEUm17kiTh7C469la/JCh61XlsZLZ3z7G3smuajG8YO3oXFqEu1ynDSllRM2RpxHTUXGy 57rusTUb77yAKd3JkkvbSetH6Bqr7G0GPm6+xCtnSDYufxzqJjL6P2+7Rtr4eQhD2gt6sCKum1x nZ7gbPsrGQv+ObO5Ugg== X-Proofpoint-ORIG-GUID: tc9Xsfq5Ub0QJZoSrxIXLC_yEPlhadB8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-16_02,2026-06-15_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 bulkscore=0 malwarescore=0 clxscore=1015 suspectscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606160094 There are two modes PDC irqchip can work in - pass through mode - secondary controller mode Secondary mode is supported depending on SoC using PDC HW Version v3.0 or higher. +------------------------------------------------------------------------+ | SoC | SM8350, SM8450 | SM8550, Hamoa | SM8650, SM8750 | |----------------------------------------------------------- ------------| | Version | v2.7 | v3.0 | v3.2 | |------------------------------------------------------------------------| | Pass through | Yes | Yes | Yes | |------------------------------------------------------------------------| | Secondary | No | Yes | Yes | +------------------------------------------------------------------------+ All PDC irqchip supports pass through mode in which both Direct SPIs and GPIO IRQs (as SPIs) are sent to GIC without latching at PDC, PDC only does inversion when needed for falling edge to rising edge or level low to level high, as the GIC do not support falling edge/level low interrupts. Newer PDCs (v3.0 onwards) also support additional secondary controller mode where PDC latches GPIO IRQs and sends to GIC as level type IRQ. Direct SPIs still works same as pass through mode without latching at PDC even in secondary controller mode. All the SoCs defaulted to pass through mode with the exception of some x1e. x1e PDC may be set to secondary controller mode for builds on CRD boards whereas it may be set to pass through mode for IoT-EVK boards. The mode configuration is done in firmware and initially shipped windows firmware did not have SCM interface to read or modify the PDC configuration. Later only write access is opened up for non secure world. Using the write access available add changes to modify the PDC mode to pass through mode via SCM write. When the write fails (on older firmware) assume to work in secondary mode. As the deepest idle state as the PDC can now wake up SoC from GPIOs and revert commit 602cb14e310a ("pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for now"). The series has been tested on x1e80100 CRD with both old and new firmware and also on kaanapali. Test conducted with tlmm-test module after applying [3] as test module needed to be fixed first. All 17/17 passes in pass through mode and 16/17 passes in secondary mode. Failing test tlmm_test_rising_while_disabled seems to be because when in irq disabled state PDC is not latching the edge interrupt. Test #1: Pass through mode on x1e80100 CRD (New firmware) root@qcom-armv8a:~# insmod tlmm-test.ko gpio=91 KTAP version 1 1..1 KTAP version 1 # Subtest: tlmm-test # module: tlmm_test 1..17 ok 1 tlmm_test_silent_rising ok 2 tlmm_test_silent_falling ok 3 tlmm_test_silent_low ok 4 tlmm_test_silent_high ok 5 tlmm_test_rising ok 6 tlmm_test_falling ok 7 tlmm_test_high ok 8 tlmm_test_low ok 9 tlmm_test_rising_in_handler ok 10 tlmm_test_falling_in_handler ok 11 tlmm_test_thread_rising ok 12 tlmm_test_thread_falling ok 13 tlmm_test_thread_high ok 14 tlmm_test_thread_low ok 15 tlmm_test_thread_rising_in_handler ok 16 tlmm_test_thread_falling_in_handler ok 17 tlmm_test_rising_while_disabled ok 1 tlmm-test Test #2: Secondary mode on x1e80100 CRD (Old firmware) root@qcom-armv8a:~# insmod tlmm-test.ko gpio=91 KTAP version 1 1..1     KTAP version 1     # Subtest: tlmm-test     # module: tlmm_test     1..17     ok 1 tlmm_test_silent_rising     ok 2 tlmm_test_silent_falling     ok 3 tlmm_test_silent_low     ok 4 tlmm_test_silent_high     ok 5 tlmm_test_rising     ok 6 tlmm_test_falling     ok 7 tlmm_test_high     ok 8 tlmm_test_low     ok 9 tlmm_test_rising_in_handler     ok 10 tlmm_test_falling_in_handler     ok 11 tlmm_test_thread_rising     ok 12 tlmm_test_thread_falling     ok 13 tlmm_test_thread_high     ok 14 tlmm_test_thread_low     ok 15 tlmm_test_thread_rising_in_handler     ok 16 tlmm_test_thread_falling_in_handler     # tlmm_test_rising_while_disabled: ASSERTION FAILED at drivers/pinctrl/qcom/tlmm-test.c:545     Expected atomic_read(&priv->intr_count) == 1, but         atomic_read(&priv->intr_count) == 0 (0x0)     not ok 17 tlmm_test_rising_while_disabled not ok 1 tlmm-test root@qcom-armv8a:~# v2 series is dependent on [1] as mostly all changes are already reviewed. v3 series is dependent on [2] which is already merged in linux-next [1] https://lore.kernel.org/linux-arm-msm/20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com/ [2] https://lore.kernel.org/linux-arm-msm/20260527095426.2324504-1-mukesh.ojha@oss.qualcomm.com/ [3] https://lore.kernel.org/linux-arm-msm/20260529-tlmm_test_changes-v1-0-88bfdccb4369@oss.qualcomm.com/ --- Changes in v3: - Add test results in cover letter with tlmm-test module - Fix coding style and struct defination - Convert raw_spin_lock to guard(raw_spin_lock) and remove _irqsave - Use bit number instead of GENMASK() for single bit fields - Use __assign_bit() and __clear_bit() APIs for single bit modifications - Use devm_ioremap() instead of ioremap() - Use devm_kcalloc() instead of kzalloc_objs() - Add separate irq chips for pass through and secondary mode IRQs - Add IRQCHIP_EOI_THREADED flag for threaded IRQ on pinctrl irqchip - Link to v2: https://patch.msgid.link/20260526-hamoa_pdc-v2-0-f6857af1ce91@oss.qualcomm.com Changes in v2: - Update to mention SoC names along with PDC versions in cover letter - Drop devicetree change to remove scm interconnects - Use qcom_scm_is_available() to wait for dependency on SCM - Drop binding change mentioning qcom,qmp and PDC config reg - Restructure version support and move all statics to struct pdc_desc - Remove pdc_enable_intr() wrapper - Differentiate direct SPI and GPIOs as SPI using PDC IRQ PARAM reg - Add changes to make PDC work in secondary controller mode - Rework and include Stephan's change to invoke irq_ack() for edge interrupt - Mention dependency via b4 prerequisites and cover letter - Link to v1: https://lore.kernel.org/r/20260312-hamoa_pdc-v1-0-760c8593ce50@oss.qualcomm.com --- To: Bjorn Andersson To: Konrad Dybcio To: Rob Herring To: Krzysztof Kozlowski To: Conor Dooley To: Thomas Gleixner To: Linus Walleij Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-gpio@vger.kernel.org Cc: Sneh Mankad Signed-off-by: Maulik Shah --- Maulik Shah (7): irqchip/qcom-pdc: restructure version support irqchip/qcom-pdc: Move all statics to struct pdc_desc irqchip/qcom-pdc: Remove pdc_enable_intr() wrapper irqchip/qcom-pdc: Differentiate between direct SPI and GPIO as SPI irqchip/qcom-pdc: Configure PDC to pass through mode Revert "pinctrl: qcom: x1e80100: Bypass PDC wakeup parent for now" arm64: dts: qcom: x1e80100: Add deepest idle state Stephan Gerhold (1): pinctrl: qcom: Acknowledge IRQs for PDC interrupt controller arch/arm64/boot/dts/qcom/hamoa.dtsi | 10 +- drivers/irqchip/qcom-pdc.c | 506 +++++++++++++++++++++++++------- drivers/pinctrl/qcom/pinctrl-msm.c | 16 +- drivers/pinctrl/qcom/pinctrl-x1e80100.c | 4 +- 4 files changed, 430 insertions(+), 106 deletions(-) --- base-commit: 8d6dbbbe3ba62de0a63e962ee004afb848c8e3ac change-id: 20260605-hamoa_pdc_v3-6dabc845021c Best regards, -- Maulik Shah