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Move all to struct pdc_desc to better align with versioning support. Document them. No functional impact. Signed-off-by: Maulik Shah --- drivers/irqchip/qcom-pdc.c | 77 ++++++++++++++++++++++++---------------------- 1 file changed, 40 insertions(+), 37 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 23276325211d..b9acb0f25c9c 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -92,15 +92,30 @@ struct pdc_irq_cfg { * @base: PDC base register for DRV2 / HLOS * @prev_base: PDC DRV1 base, applicable only for x1e RTL bug. * @version: PDC version + * @region: PDC interrupt continuous range + * @region_cnt: Total PDC ranges + * @x1e_quirk: x1e H/W Bug handling + * @lock: lock for IRQ_ENABLE_BANK protection * @regs: PDC regs (IRQ_ENABLE_BANK and IRQ_CFG) * @cfg_fields: Fields of IRQ_CFG reg + * @enable_intr: pointer to enable function based on PDC version */ struct pdc_desc { void __iomem *base; void __iomem *prev_base; u32 version; + + struct pdc_pin_region *region; + int region_cnt; + + bool x1e_quirk; + + raw_spinlock_t lock; + const struct pdc_regs *regs; const struct pdc_irq_cfg *cfg_fields; + + void (*enable_intr)(int pin_out, bool on); }; static const struct pdc_regs pdc_v3_2 = { @@ -138,11 +153,6 @@ struct pdc_pin_region { #define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base) -static DEFINE_RAW_SPINLOCK(pdc_lock); -static struct pdc_pin_region *pdc_region; -static int pdc_region_cnt; -static unsigned int pdc_version; -static bool pdc_x1e_quirk; static struct pdc_desc *pdc; static void pdc_base_reg_write(void __iomem *base, int reg, u32 i, u32 val) @@ -199,7 +209,7 @@ static void pdc_enable_intr_bank(int pin_out, bool on) enable = pdc_reg_read(pdc->regs->irq_en_reg, index); __assign_bit(mask, &enable, on); - if (pdc_x1e_quirk) + if (pdc->x1e_quirk) pdc_x1e_irq_enable_write(index, enable); else pdc_reg_write(pdc->regs->irq_en_reg, index, enable); @@ -213,21 +223,11 @@ static void pdc_enable_intr_cfg(int pin_out, bool on) pdc_reg_write(pdc->regs->irq_cfg_reg, pin_out, enable); } -static void __pdc_enable_intr(int pin_out, bool on) -{ - if (pdc_version < PDC_VERSION_3_2) - pdc_enable_intr_bank(pin_out, on); - else - pdc_enable_intr_cfg(pin_out, on); -} - static void pdc_enable_intr(struct irq_data *d, bool on) { - unsigned long flags; + guard(raw_spinlock)(&pdc->lock); - raw_spin_lock_irqsave(&pdc_lock, flags); - __pdc_enable_intr(d->hwirq, on); - raw_spin_unlock_irqrestore(&pdc_lock, flags); + pdc->enable_intr(d->hwirq, on); } static void qcom_pdc_gic_disable(struct irq_data *d) @@ -350,12 +350,10 @@ static struct irq_chip qcom_pdc_gic_chip = { static struct pdc_pin_region *get_pin_region(int pin) { - int i; - - for (i = 0; i < pdc_region_cnt; i++) { - if (pin >= pdc_region[i].pin_base && - pin < pdc_region[i].pin_base + pdc_region[i].cnt) - return &pdc_region[i]; + for (int i = 0; i < pdc->region_cnt; i++) { + if (pin >= pdc->region[i].pin_base && + pin < pdc->region[i].pin_base + pdc->region[i].cnt) + return &pdc->region[i]; } return NULL; @@ -411,39 +409,39 @@ static const struct irq_domain_ops qcom_pdc_ops = { static int pdc_setup_pin_mapping(struct device *dev, struct device_node *np) { - int ret, n, i; + int ret, n; n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32)); if (n <= 0 || n % 3) return -EINVAL; - pdc_region_cnt = n / 3; - pdc_region = devm_kcalloc(dev, pdc_region_cnt, sizeof(*pdc_region), - GFP_KERNEL); - if (!pdc_region) { - pdc_region_cnt = 0; + pdc->region_cnt = n / 3; + pdc->region = devm_kcalloc(dev, pdc->region_cnt, sizeof(*pdc->region), + GFP_KERNEL); + if (!pdc->region) { + pdc->region_cnt = 0; return -ENOMEM; } - for (n = 0; n < pdc_region_cnt; n++) { + for (n = 0; n < pdc->region_cnt; n++) { ret = of_property_read_u32_index(np, "qcom,pdc-ranges", n * 3 + 0, - &pdc_region[n].pin_base); + &pdc->region[n].pin_base); if (ret) return ret; ret = of_property_read_u32_index(np, "qcom,pdc-ranges", n * 3 + 1, - &pdc_region[n].parent_base); + &pdc->region[n].parent_base); if (ret) return ret; ret = of_property_read_u32_index(np, "qcom,pdc-ranges", n * 3 + 2, - &pdc_region[n].cnt); + &pdc->region[n].cnt); if (ret) return ret; - for (i = 0; i < pdc_region[n].cnt; i++) - __pdc_enable_intr(i + pdc_region[n].pin_base, 0); + for (int i = 0; i < pdc->region[n].cnt; i++) + pdc->enable_intr(i + pdc->region[n].pin_base, 0); } return 0; @@ -481,13 +479,16 @@ static int qcom_pdc_probe(struct platform_device *pdev, struct device_node *pare if (pdc->version >= PDC_VERSION_3_2) { pdc->cfg_fields = &pdc_cfg_v3_2; pdc->regs = &pdc_v3_2; + pdc->enable_intr = pdc_enable_intr_cfg; } else if (pdc->version < PDC_VERSION_3_2 && pdc->version >= PDC_VERSION_3_0) { pdc->cfg_fields = &pdc_cfg_v3_0; pdc->regs = &pdc_v3_0; + pdc->enable_intr = pdc_enable_intr_bank; } else { pdc->cfg_fields = &pdc_cfg_v2_7; pdc->regs = &pdc_v2_7; + pdc->enable_intr = pdc_enable_intr_bank; } /* @@ -506,7 +507,7 @@ static int qcom_pdc_probe(struct platform_device *pdev, struct device_node *pare return -ENXIO; } - pdc_x1e_quirk = true; + pdc->x1e_quirk = true; } parent_domain = irq_find_host(parent); @@ -521,6 +522,8 @@ static int qcom_pdc_probe(struct platform_device *pdev, struct device_node *pare return ret; } + raw_spin_lock_init(&pdc->lock); + pdc_domain = irq_domain_create_hierarchy(parent_domain, IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP, PDC_MAX_IRQS, -- 2.43.0