From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E58E21EDA32 for ; Tue, 16 Jun 2026 13:20:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781616041; cv=none; b=EH05aipP7b2v1UJWe+WpRPoPoTZL9mEp3ZBSKSzTCcqIuE6jM79+zIPh/w7kBy1Kj0VdFXqYmCoNXOinx0fzS5XobCRmHxLVhaj0VeLaG7X6R9fzWzIrZu/9TxmtFGOvF+9Z+emaqyYiZGVYJ9HW6hBqDT/KEbUU4MHSOLty114= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781616041; c=relaxed/simple; bh=yQj4xK1aUesgkelr6CeBnukHIeH9ZEw+Y4T3VxRf54w=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=t0jKUruJ+ERcIdiXozLUupcdwYNdJ3Bc+v3O2lgajNOqLKCOCU+QVsqkMhfOq2gr1yWjqfQb+jzTlJuYGdKXwl60ers8HyexQJKPdhrJ03MbdgTtlC8CSBTqVb7mOce0aRxCPOAGoFtfoDo+691UO5h87MJiNN7o/Z8mOC9aX6o= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=donh8VbK; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Lyitqn9n; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="donh8VbK"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Lyitqn9n" Date: Tue, 16 Jun 2026 15:20:36 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1781616038; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=hK1URbWMjTSwREeJuMk0dZQdbDdhk6I3Ww8egTfiPQA=; b=donh8VbKIVMw8gx2Dolidy+LVg5ziBkQ6VW7/eye0RQBOi3RyJ3JN/K2hx4v6o8YxRi4As rea99dJ4ZeKw2Q4vBQeX8rn64JF6nHpMcUxwe7Cs0iGjbc/fo1d9VgU8d40V6q9XA6uYZc ltLEzWOxozu+ZrWyxN1ACa7O9mkZ3WDA2uZhv1P4S9Db+gb6GRCYF846l3pPesPhdkylbr ngMdesejEnUOGwnjO9gQ5oH8aYvijeLTKB6jHU1xzwg4bgCRm9kz0rqI4jvy9L3Q0iCdFe pQ4AdlkvE00cHMGCTyIM6UPQTGPRKxCYlSYimJDiDhMiticR2P09FqoAqSDeCQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1781616038; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=hK1URbWMjTSwREeJuMk0dZQdbDdhk6I3Ww8egTfiPQA=; b=Lyitqn9n1ObXNFQsF/9R0Wp3Tr+yo6P8R+S78gdfFbIAAlZLX4xOGIePfGANhzJ56ZVi42 Rlp6PNIOPkw1krAA== From: Sebastian Andrzej Siewior To: Chuyi Zhou Cc: tglx@kernel.org, mingo@redhat.com, luto@kernel.org, peterz@infradead.org, paulmck@kernel.org, muchun.song@linux.dev, bp@alien8.de, dave.hansen@linux.intel.com, pbonzini@redhat.com, clrkwllms@kernel.org, rostedt@goodmis.org, nadav.amit@gmail.com, vkuznets@redhat.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH v8 11/14] x86/mm: Cap flush_tlb_info alignment at 64 bytes Message-ID: <20260616132036.A4j5OW-H@linutronix.de> References: <20260616111127.966468-1-zhouchuyi@bytedance.com> <20260616111127.966468-12-zhouchuyi@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20260616111127.966468-12-zhouchuyi@bytedance.com> On 2026-06-16 19:11:24 [+0800], Chuyi Zhou wrote: > A stack allocated flush_tlb_info should keep cacheline alignment to > avoid the regression that motivated the per-CPU storage, but using > SMP_CACHE_BYTES directly can make the stack frame grow excessively on > configurations with large cache lines[1]. > > Add FLUSH_TLB_INFO_ALIGN and cap the type alignment at 64 bytes. The > existing per-CPU flush_tlb_info instance remains > DEFINE_PER_CPU_SHARED_ALIGNED(), so its per-CPU shared-cacheline > alignment is unchanged. > > The capped type alignment matters once flush_tlb_info is moved back to the > stack by the next patch. > > link[1]: https://lore.kernel.org/all/tip-780e0106d468a2962b16b52fdf42898f2639e0a0@git.kernel.org/ I suggest to incorporate a reference such as | See commit 780e0106d468a ("x86/mm/tlb: Revert "x86/mm: Align TLB | invalidation info"") where the usage of SMP_CACHE_BYTES led to 320 bytes | stack consumption. This [1] and link and such is just forth and back. > Signed-off-by: Chuyi Zhou Other than that, Reviewed-by: Sebastian Andrzej Siewior Sebastian