From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F367C47A0B4 for ; Tue, 16 Jun 2026 17:03:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.42 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781629398; cv=none; b=roUFGGnS5almVTnozBJp2OfusGND6klqAY83Xl6KGH6AgYCAEVVM6DvCMgswQzvUwvwtICeaNoHJSRRJHQmbjtQxtv7B45/GBEc9QSON3ZN4CJrurUy328Qd5ECmHjRSil9ahw04U0YQIg7oc2p4MqMCSnDDKjHtBBVt3MtNBRQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781629398; c=relaxed/simple; bh=0yzyptuVzsPPA3OB4pIn9FZo3PcfjkK4v2swSq7IYjk=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=liCnz/+UThq28kI9WI8DgdGTf85Wah/jgHEUdr3kN2zZx7PdyH6UX+ag8g/davgAyVlge8wtSrGNUL3LW/doPaVeleP9m0Y2R6UvVrQkOAlH2y2IY/IZEaDnwGNlGmxe59GKJFFTgcCTNLvLdXkRhn2ZiWHvOEBH2eLdJCzaSEE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=s9dVHWXf; arc=none smtp.client-ip=209.85.221.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="s9dVHWXf" Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-4600ddc4017so3648308f8f.0 for ; Tue, 16 Jun 2026 10:03:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1781629395; x=1782234195; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=A04Lmah/qwZcgFC/+pc71aXlgIrJ+yhib0Ydg9Jehl4=; b=s9dVHWXfLqCnJwVFd8LOr8xuvYSoPI1QSNq/hXtgq0Pi16iyCIV667KI9/EuJ3YswV 1kCTgLHe+5aA2m2Qs+DuAovvdplSmnjJAansiQ0yGwI9smrnhNoaS6xKf1z/8sq0XDqk 2YaHdG3LxkBdqzzeTl0/NU+95pPII4guZ5MQ9rOQo4Tfr6WiL97l9I1hpDh+JNO8xuKj SWkqiIzSw7N8VkscfIBhiJmj3LMJxW65+w5iX+cWgwb9YPG4dsFjpkFOK9HdcMCE0Fom XryH2qt+aGkXwcrhvOjRVjoFVKwjlrqXQAHzUAmhIa6jG6NL47SUthWmZl4XTxmrAj3o 7ViQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781629395; x=1782234195; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=A04Lmah/qwZcgFC/+pc71aXlgIrJ+yhib0Ydg9Jehl4=; b=IrxR6NtHq6n4T71bZ+h3FhfYfrgWkSQ3UbBRLocx6XVRU+wB11UuAzNEX8Of3aBh/n 4Oh9FdbDq82YU+ksyuIC3XvnI4jXo7nnQ5ounheF+bHDA1e+ABklhjTrO7Rv0P1wLZH7 aQ/c0Qu37irJwEaKptz2T9z1ZXtbgmnvD++GDV/xj7b1Y02aQhhMnwisUbO9psx9ZKn5 dwsOg1yAaNklWGQsJ3VTv9HS97YEOWqPoXaV/bp6a+q89jCN4indCSNezX0qFeC+5Rji yaUHuT1Kz6Qa36Q0Q+ssQVb/I4A4M14AvXqRZKGY6VvyElp0oGrAWsyH6ZN/D4iFXIWU G+Xw== X-Gm-Message-State: AOJu0YzhdP531wIZUV9AOE7xzlVjgNJwmuk7XWlCsRUDwoeV/JNMEESj m61ILVv4c1DuhClgFKdLD5ShMlhQawepi7q3UssgB/1EUDY996RPwbLM X-Gm-Gg: Acq92OGW20bTc2FYvAqYgQyrsKXyUVqVN6RqC9j2Edkb1HR2994fXEo8uHbmRmGmJvi MxdfqsQ7ebRmV0SVqaub5XM94Kcm3OeCwiqTcjtL104p21Qrf1bGAfx4zZeG51budUOIMl0xlrR VUQyrU9+GrUhZWLGcXDphe2DsULbLsE4az9VknX3U39ni1JTbzs4VLPU2iEumEQKesmcWOQVAVs ysUOD1vcxEasSDHqmrkGs7Bnts6FuawJWs+G4siCRy70DVB47YPJZ+hEMCH2/G/pvS1xuAI3/Pd ExPYGMgCk9IP5EAywQBl5L/w6tN5yYJF5gt2Fw5IdRmOUhSaLgstlb6BbXxiFmU4cInvm71xoPr HAFJzh7tJ6dFIV7gZdazWUbS2/6impFS4n6c/dY32k6UKNliPLSEFDPNbccMrLix9eaHcSOfEL8 yZ9gvgNVhNL24ZXCot1HY/kK/EggD7xBXIxR7X0R9/p/97y7Uu1zjz1ZwaVtIn93DBF5stkbF2c w== X-Received: by 2002:a05:600c:2e44:b0:490:9588:bdae with SMTP id 5b1f17b1804b1-492333ca38dmr4086305e9.18.1781629395279; Tue, 16 Jun 2026 10:03:15 -0700 (PDT) Received: from fedora ([196.77.26.11]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49230a4fd31sm78366005e9.4.2026.06.16.10.03.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 10:03:14 -0700 (PDT) From: Jad Keskes To: Mark Brown , Chanwoo Choi , Krzysztof Kozlowski , Liam Girdwood , Lee Jones Cc: linux-kernel@vger.kernel.org, Jad Keskes Subject: [PATCH v3] regulator: max14577: fix set_mode clobbering enable on MAX77836 LDOs Date: Tue, 16 Jun 2026 18:02:56 +0100 Message-ID: <20260616170256.1659595-1-inasj268@gmail.com> X-Mailer: git-send-email 2.54.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit So the PWRMD field in CNFG1_LDO is both the enable bit and the mode. You can't change one without stepping on the other. The problem is that enable() from the regulator core just writes enable_mask (which is PWRMD_NORMAL). If you'd called set_mode(LPM) then disabled and re-enabled, the mode gets reset to NORMAL. And set_mode updates the register through the same field, so it can accidentally enable a disabled regulator. Fix it by storing the mode in per-regulator data. A custom enable writes whatever mode was last set. set_mode only touches hardware if the regulator is already on; otherwise it just caches the value. Add of_map_mode while here so the initial mode can be wired from DT. Signed-off-by: Jad Keskes --- v3: - Cache the desired mode in driver data instead of writing to the enable register directly, so enable() and set_mode() stop fighting over the same register field (caught by Mark Brown). - Add custom enable/disable that respect the cached mode. - Add of_map_mode while here. Link: https://lore.kernel.org/all/81002c3a-f868-494c-83b1-9cf6214255b5@sirena.org.uk/ drivers/regulator/max14577-regulator.c | 103 ++++++++++++++++++++++++- include/linux/mfd/max14577-private.h | 3 + 2 files changed, 102 insertions(+), 4 deletions(-) diff --git a/drivers/regulator/max14577-regulator.c b/drivers/regulator/max14577-regulator.c index c9d8d5e31cbd..378475368356 100644 --- a/drivers/regulator/max14577-regulator.c +++ b/drivers/regulator/max14577-regulator.c @@ -123,15 +123,89 @@ static const struct regulator_desc max14577_supported_regulators[] = { [MAX14577_CHARGER] = MAX14577_CHARGER_REG, }; +struct max77836_ldo { + struct max14577 *max14577; + unsigned int mode; +}; + +static int max77836_ldo_enable(struct regulator_dev *rdev) +{ + struct max77836_ldo *ldo = rdev_get_drvdata(rdev); + + return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, + MAX77836_CNFG1_LDO_PWRMD_MASK, ldo->mode); +} + +static int max77836_ldo_disable(struct regulator_dev *rdev) +{ + return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, + MAX77836_CNFG1_LDO_PWRMD_MASK, + MAX77836_CNFG1_LDO_PWRMD_OFF); +} + +static unsigned int max77836_ldo_get_mode(struct regulator_dev *rdev) +{ + struct max77836_ldo *ldo = rdev_get_drvdata(rdev); + + switch (ldo->mode) { + case MAX77836_CNFG1_LDO_PWRMD_LPM: + return REGULATOR_MODE_IDLE; + case MAX77836_CNFG1_LDO_PWRMD_NORMAL: + return REGULATOR_MODE_NORMAL; + default: + return REGULATOR_MODE_INVALID; + } +} + +static int max77836_ldo_set_mode(struct regulator_dev *rdev, + unsigned int mode) +{ + struct max77836_ldo *ldo = rdev_get_drvdata(rdev); + unsigned int val; + + switch (mode) { + case REGULATOR_MODE_NORMAL: + val = MAX77836_CNFG1_LDO_PWRMD_NORMAL; + break; + case REGULATOR_MODE_IDLE: + val = MAX77836_CNFG1_LDO_PWRMD_LPM; + break; + default: + return -EINVAL; + } + + ldo->mode = val; + + /* Only touch hardware if the regulator is already on */ + if (regulator_is_enabled_regmap(rdev)) + return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, + MAX77836_CNFG1_LDO_PWRMD_MASK, val); + + return 0; +} + +static unsigned int max77836_ldo_of_map_mode(unsigned int mode) +{ + switch (mode) { + case REGULATOR_MODE_NORMAL: + case REGULATOR_MODE_IDLE: + return mode; + default: + return REGULATOR_MODE_INVALID; + } +} + static const struct regulator_ops max77836_ldo_ops = { .is_enabled = regulator_is_enabled_regmap, - .enable = regulator_enable_regmap, - .disable = regulator_disable_regmap, + .enable = max77836_ldo_enable, + .disable = max77836_ldo_disable, .list_voltage = regulator_list_voltage_linear, .map_voltage = regulator_map_voltage_linear, .get_voltage_sel = regulator_get_voltage_sel_regmap, .set_voltage_sel = regulator_set_voltage_sel_regmap, - /* TODO: add .set_suspend_mode */ + .get_mode = max77836_ldo_get_mode, + .set_mode = max77836_ldo_set_mode, + .of_map_mode = max77836_ldo_of_map_mode, }; #define MAX77836_LDO_REG(num) { \ @@ -205,7 +279,6 @@ static int max14577_regulator_probe(struct platform_device *pdev) } config.dev = max14577->dev; - config.driver_data = max14577; for (i = 0; i < supported_regulators_size; i++) { struct regulator_dev *regulator; @@ -217,6 +290,28 @@ static int max14577_regulator_probe(struct platform_device *pdev) config.init_data = pdata->regulators[i].initdata; config.of_node = pdata->regulators[i].of_node; } + + /* + * LDOs need per-regulator driver data to store their mode. + * The charger and safeout share the core MFD struct. + */ + if (dev_type == MAXIM_DEVICE_TYPE_MAX77836 && + (supported_regulators[i].id == MAX77836_LDO1 || + supported_regulators[i].id == MAX77836_LDO2)) { + struct max77836_ldo *ldo; + + ldo = devm_kzalloc(&pdev->dev, sizeof(*ldo), + GFP_KERNEL); + if (!ldo) + return -ENOMEM; + + ldo->max14577 = max14577; + ldo->mode = MAX77836_CNFG1_LDO_PWRMD_NORMAL; + config.driver_data = ldo; + } else { + config.driver_data = max14577; + } + config.regmap = max14577_get_regmap(max14577, supported_regulators[i].id); diff --git a/include/linux/mfd/max14577-private.h b/include/linux/mfd/max14577-private.h index dd51a37fa37f..5957e15b568e 100644 --- a/include/linux/mfd/max14577-private.h +++ b/include/linux/mfd/max14577-private.h @@ -350,6 +350,9 @@ enum max77836_pmic_reg { #define MAX77836_CNFG1_LDO_PWRMD_SHIFT 6 #define MAX77836_CNFG1_LDO_TV_SHIFT 0 #define MAX77836_CNFG1_LDO_PWRMD_MASK (0x3 << MAX77836_CNFG1_LDO_PWRMD_SHIFT) +#define MAX77836_CNFG1_LDO_PWRMD_OFF (0x0 << MAX77836_CNFG1_LDO_PWRMD_SHIFT) +#define MAX77836_CNFG1_LDO_PWRMD_LPM (0x1 << MAX77836_CNFG1_LDO_PWRMD_SHIFT) +#define MAX77836_CNFG1_LDO_PWRMD_NORMAL (0x3 << MAX77836_CNFG1_LDO_PWRMD_SHIFT) #define MAX77836_CNFG1_LDO_TV_MASK (0x3f << MAX77836_CNFG1_LDO_TV_SHIFT) /* LDO1/LDO2 CONFIG2 register */ -- 2.54.0