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Tue, 16 Jun 2026 13:14:56 -0700 (PDT) Received: from hu-mohs-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c4328abe7bsm136385985ad.49.2026.06.16.13.14.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Jun 2026 13:14:56 -0700 (PDT) From: Mohammad Rafi Shaik To: Srinivas Kandagatla , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-sound@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Harendra Gautam Subject: [PATCH v1 2/8] arm64: dts: qcom: shikra: Add QAIF CPU node for audio Date: Wed, 17 Jun 2026 01:43:09 +0530 Message-Id: <20260616201315.2565115-3-mohammad.rafi.shaik@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260616201315.2565115-1-mohammad.rafi.shaik@oss.qualcomm.com> References: <20260616201315.2565115-1-mohammad.rafi.shaik@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=SoCgLvO0 c=1 sm=1 tr=0 ts=6a31aec1 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=u7cSe3xy4d7cT3VL5CEA:9 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: fgJszSw8DbjvCnVSymmygGMxpT4QSb_d X-Proofpoint-ORIG-GUID: fgJszSw8DbjvCnVSymmygGMxpT4QSb_d X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE2MDIwNSBTYWx0ZWRfX+7TYO3MUvoOb jrLmav5fxWiFTp2X1KqLlP1o3GOQMeDYXuU49ztZOW+VKMDqOr+u+RjaPs/g22T/11f0SIimaXE tfdrH+kmcWUTiT6RWmnmNzJvcTWv2CY8qvcuA7Kee5yLhI1gTFEJoY820S8AfCE0wKMCUUzuvyw B93Rzv0UJO2835BTj9iV4O7VfAf1PsSzLg2BtxkodFG+4fROYeFowW8zkkOJXVeqHwVffXHbPhg oeyP4XSmxaf0zlQr+84zhtrEv37tl8fc2YjEVLscianfBsAjRVgNewdYAwmdIAd26pqtSleCPYM lDMofcQAtGvMHuknzruuYfycsvvTFMDa5S/muwFUDl3X38yTM7Egyllv9kT4/PfTG7J6ncoxfEA 4r0w9UL/ebxs63mK2qND8yiIo9seVGJngTluf7NGsOp4kzvFGPe2nc9XIQmSAid0jQNo4kadUrs ApRbGYCoeBq+RZ5qtaw== X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE2MDIwNSBTYWx0ZWRfXwc+adzFregg8 v8RH2i6KCzzdFRKMX/tjnJveypIHEKLCAzKkbFcbceTxP4yHtEiLY6XLRQbByNNSwRJAG/9hUo0 m5gCeAKu8SpNcw8+19+dfBGz6Uip1GY= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-16_05,2026-06-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 clxscore=1015 spamscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606160205 Add the QAIF CPU endpoint in shikra.dtsi so board files can connect LPASS front-end links to backend codecs. Describe the MMIO region, interrupt, IOMMU mapping and required clocks for the QAIF block. Keep the node disabled at SoC level; board dts files enable and consume it in subsequent patches. Co-developed-by: Harendra Gautam Signed-off-by: Harendra Gautam Signed-off-by: Mohammad Rafi Shaik --- arch/arm64/boot/dts/qcom/shikra.dtsi | 46 ++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index bc4ad2bcbbec..e58c87fc8cb0 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -2017,6 +2017,52 @@ dispcc: clock-controller@5f00000 { #power-domain-cells = <1>; }; + qaif_cpu: audio@a000000 { + compatible = "qcom,shikra-qaif-cpu"; + reg = <0x0 0x0a000000 0x0 0x20000>; + + interrupts = ; + + clocks = <&gcc GCC_LPASS_CONFIG_CLK>, + <&gcc GCC_LPASS_CORE_AXIM_CLK>, + <&audiocorecc AUDIO_CORE_CC_AUD_DMA_CLK>, + <&audiocorecc AUDIO_CORE_CC_AUD_DMA_MEM_CLK>, + <&audiocorecc AUDIO_CORE_CC_BUS_CLK>, + <&audiocorecc AUDIO_CORE_CC_AIF_IF0_EBIT_CLK>, + <&audiocorecc AUDIO_CORE_CC_AIF_IF0_IBIT_CLK>, + <&audiocorecc AUDIO_CORE_CC_AIF_IF1_EBIT_CLK>, + <&audiocorecc AUDIO_CORE_CC_AIF_IF1_IBIT_CLK>, + <&audiocorecc AUDIO_CORE_CC_AIF_IF2_EBIT_CLK>, + <&audiocorecc AUDIO_CORE_CC_AIF_IF2_IBIT_CLK>, + <&audiocorecc AUDIO_CORE_CC_AIF_IF3_EBIT_CLK>, + <&audiocorecc AUDIO_CORE_CC_AIF_IF3_IBIT_CLK>, + <&audiocorecc AUDIO_CORE_CC_EXT_MCLKA_OUT_CLK>, + <&audiocorecc AUDIO_CORE_CC_EXT_MCLKB_OUT_CLK>; + clock-names = "lpass_config_clk", + "lpass_core_axim_clk", + "aud_dma_clk", + "aud_dma_mem_clk", + "bus_clk", + "aif_if0_ebit_clk", + "aif_if0_ibit_clk", + "aif_if1_ebit_clk", + "aif_if1_ibit_clk", + "aif_if2_ebit_clk", + "aif_if2_ibit_clk", + "aif_if3_ebit_clk", + "aif_if3_ibit_clk", + "ext_mclka_clk", + "ext_mclkb_clk"; + + iommus = <&apps_smmu 0x1c0 0x0>; + + #sound-dai-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + audiocorecc: clock-controller@a0a0000 { compatible = "qcom,shikra-cqm-audiocorecc"; reg = <0x0 0x0a0a0000 0x0 0x10000>, -- 2.34.1