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This controller supports parallel camera sensors and enables image data capture through a parallel interface. Signed-off-by: Alice Yuan Signed-off-by: Robert Chiras Signed-off-by: Zhipeng Wang Signed-off-by: Frank Li --- Change in v5 - Use subdev_1to1 register function - Use v4l2_subdev_get_frame_desc_passthrough - Use dwc csi2 similar logic enable/disable stream - Add route settup at imx_cpi_init_state() - Remove V2 register layout support, add it later change in v4 - remove unnecesary header file. - use devm_bulk_clk_get(). - update kConfig i.MX8/i.MX9 - Remove define IMX_CPI_DEF_PIX_WIDTH ..., which used once only - drop get_interface_ctrl_reg1_param - drop uv-swap - drop imx_cpi_link_setup by use immutable link. - use enable/disable_stream() replace depericated .s_stream. - remove dbg print and reg dump functions. - use goto/.remove() to do manual cleanup. - remove imx93 support. Add it later. change in v3 - replace csi with cpi - use __free(fwnode_handle) to simpilfy code - remove imx91 driver data, which is the same as imx93 change in v2 - remove MODULE_ALIAS - use devm_pm_runtime_enable() and cleanup remove function - change output format to 1x16. controller convert 2x8 to 1x16 format --- MAINTAINERS | 1 + drivers/media/platform/nxp/Kconfig | 12 + drivers/media/platform/nxp/Makefile | 1 + drivers/media/platform/nxp/imx-parallel-cpi.c | 614 ++++++++++++++++++++++++++ 4 files changed, 628 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index deeec900ad071..e28b395734ef5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16263,6 +16263,7 @@ F: Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml F: Documentation/devicetree/bindings/media/nxp,imx7-csi.yaml F: Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml F: drivers/media/platform/nxp/imx-mipi-csis.c +F: drivers/media/platform/nxp/imx-parallel-cpi.c F: drivers/media/platform/nxp/imx7-media-csi.c F: drivers/media/platform/nxp/imx8mq-mipi-csi2.c diff --git a/drivers/media/platform/nxp/Kconfig b/drivers/media/platform/nxp/Kconfig index 40e3436669e21..90f7c792003f2 100644 --- a/drivers/media/platform/nxp/Kconfig +++ b/drivers/media/platform/nxp/Kconfig @@ -39,6 +39,18 @@ config VIDEO_IMX_MIPI_CSIS Video4Linux2 sub-device driver for the MIPI CSI-2 CSIS receiver v3.3/v3.6.3 found on some i.MX7 and i.MX8 SoCs. +config VIDEO_IMX_PARALLEL_CPI + tristate "NXP i.MX8/i.MX9 Parallel CPI Driver" + depends on ARCH_MXC || COMPILE_TEST + depends on VIDEO_DEV + select MEDIA_CONTROLLER + select V4L2_1TO1 + select V4L2_FWNODE + select VIDEO_V4L2_SUBDEV_API + help + Video4Linux2 sub-device driver for PARALLEL CPI receiver found + on some iMX8 and iMX9 SoCs. + source "drivers/media/platform/nxp/imx8-isi/Kconfig" # mem2mem drivers diff --git a/drivers/media/platform/nxp/Makefile b/drivers/media/platform/nxp/Makefile index 4d90eb7136525..5346919d2f108 100644 --- a/drivers/media/platform/nxp/Makefile +++ b/drivers/media/platform/nxp/Makefile @@ -7,5 +7,6 @@ obj-y += imx8-isi/ obj-$(CONFIG_VIDEO_IMX7_CSI) += imx7-media-csi.o obj-$(CONFIG_VIDEO_IMX8MQ_MIPI_CSI2) += imx8mq-mipi-csi2.o obj-$(CONFIG_VIDEO_IMX_MIPI_CSIS) += imx-mipi-csis.o +obj-$(CONFIG_VIDEO_IMX_PARALLEL_CPI) += imx-parallel-cpi.o obj-$(CONFIG_VIDEO_IMX_PXP) += imx-pxp.o obj-$(CONFIG_VIDEO_MX2_EMMAPRP) += mx2_emmaprp.o diff --git a/drivers/media/platform/nxp/imx-parallel-cpi.c b/drivers/media/platform/nxp/imx-parallel-cpi.c new file mode 100644 index 0000000000000..00f5d5f47644b --- /dev/null +++ b/drivers/media/platform/nxp/imx-parallel-cpi.c @@ -0,0 +1,614 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * i.MX Parallel CPI receiver driver. + * + * Copyright 2019-2025 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* CI_PI INTERFACE CONTROL */ +#define IF_CTRL_REG_PL_ENABLE BIT(0) +#define IF_CTRL_REG_PL_VALID BIT(1) +#define IF_CTRL_REG_DATA_TYPE_SEL BIT(8) +#define IF_CTRL_REG_DATA_TYPE(x) FIELD_PREP(GENMASK(13, 9), (x)) + +#define DATA_TYPE_OUT_NULL 0x00 +#define DATA_TYPE_OUT_RGB 0x04 +#define DATA_TYPE_OUT_YUV444 0x08 +#define DATA_TYPE_OUT_YYU420_ODD 0x10 +#define DATA_TYPE_OUT_YYU420_EVEN 0x12 +#define DATA_TYPE_OUT_YYY_ODD 0x18 +#define DATA_TYPE_OUT_UYVY_EVEN 0x1a +#define DATA_TYPE_OUT_RAW 0x1c + +#define IF_CTRL_REG_IF_FORCE_HSYNV_OVERRIDE 0x4 +#define IF_CTRL_REG_IF_FORCE_VSYNV_OVERRIDE 0x2 +#define IF_CTRL_REG_IF_FORCE_DATA_ENABLE_OVERRIDE 0x1 + +/* CPI INTERFACE CONTROL REG */ +#define CPI_CTRL_REG_CPI_EN BIT(0) +#define CPI_CTRL_REG_PIXEL_CLK_POL BIT(1) +#define CPI_CTRL_REG_HSYNC_POL BIT(2) +#define CPI_CTRL_REG_VSYNC_POL BIT(3) +#define CPI_CTRL_REG_DE_POL BIT(4) +#define CPI_CTRL_REG_PIXEL_DATA_POL BIT(5) +#define CPI_CTRL_REG_CCIR_EXT_VSYNC_EN BIT(6) +#define CPI_CTRL_REG_CCIR_EN BIT(7) +#define CPI_CTRL_REG_CCIR_VIDEO_MODE BIT(8) +#define CPI_CTRL_REG_CCIR_NTSC_EN BIT(9) +#define CPI_CTRL_REG_CCIR_VSYNC_RESET_EN BIT(10) +#define CPI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN BIT(11) +#define CPI_CTRL_REG_HSYNC_FORCE_EN BIT(12) +#define CPI_CTRL_REG_VSYNC_FORCE_EN BIT(13) +#define CPI_CTRL_REG_GCLK_MODE_EN BIT(14) +#define CPI_CTRL_REG_VALID_SEL BIT(15) +#define CPI_CTRL_REG_RAW_OUT_SEL BIT(16) +#define CPI_CTRL_REG_HSYNC_OUT_SEL BIT(17) +#define CPI_CTRL_REG_HSYNC_PULSE(x) FIELD_PREP(GENMASK(21, 19), (x)) +#define CPI_CTRL_REG_UV_SWAP_EN BIT(22) +#define CPI_CTRL_REG_DATA_TYPE_IN(x) FIELD_PREP(GENMASK(26, 23), (x)) +#define CPI_CTRL_REG_MASK_VSYNC_COUNTER(x) FIELD_PREP(GENMASK(28, 27), (x)) +#define CPI_CTRL_REG_SOFTRST BIT(31) + +/* CPI INTERFACE STATUS */ +#define CPI_STATUS_FIELD_TOGGLE BIT(0) +#define CPI_STATUS_ECC_ERROR BIT(1) + +/* CPI INTERFACE CONTROL REG1 */ +#define CPI_CTRL_REG1_PIXEL_WIDTH(v) FIELD_PREP(GENMASK(15, 0), (v)) +#define CPI_CTRL_REG1_VSYNC_PULSE(v) FIELD_PREP(GENMASK(31, 16), (v)) + +#define CPI_CTRL_V2_REG1_PIXEL_WIDTH(v) FIELD_PREP(GENMASK(16, 0), (v)) +#define CPI_CTRL_V2_REG1_VSYNC_PULSE(v) FIELD_PREP(GENMASK(31, 16), (v)) + +/* Need match field DATA_TYPE_IN definition at CPI CTRL register */ +enum cpi_in_data_type { + CPI_IN_DT_UYVY_BT656_8 = 0x0, + CPI_IN_DT_UYVY_BT656_10, + CPI_IN_DT_RGB_8, + CPI_IN_DT_BGR_8, + CPI_IN_DT_YVYU_8 = 0x5, + CPI_IN_DT_YUV_8, + CPI_IN_DT_RAW_8 = 0x9, + CPI_IN_DT_RAW_10, +}; + +enum { + PI_GATE_CLOCK_MODE, + PI_CCIR_MODE, +}; + +enum { + PI_V1, +}; + +struct imx_cpi_plat_data { + u32 version; + u32 if_ctrl_reg; + u32 interface_status; + u32 interface_ctrl_reg; + u32 interface_ctrl_reg1; +}; + +struct imx_cpi_device { + struct device *dev; + void __iomem *regs; + struct clk_bulk_data *clks; + int num_clks; + + struct v4l2_subdev_1to1 sd_1to1; + + const struct imx_cpi_plat_data *pdata; + + u32 enabled_streams; + u8 mode; +}; + +struct imx_cpi_pix_format { + u32 code; + u32 output; + u32 data_type; + u8 width; +}; + +static const struct imx_cpi_pix_format imx_cpi_formats[] = { + /* YUV formats. */ + { + .code = MEDIA_BUS_FMT_UYVY8_2X8, + .output = MEDIA_BUS_FMT_UYVY8_1X16, + .data_type = CPI_IN_DT_UYVY_BT656_8, + .width = 16, + }, { + .code = MEDIA_BUS_FMT_YUYV8_2X8, + .output = MEDIA_BUS_FMT_YUYV8_1X16, + .data_type = CPI_IN_DT_YVYU_8, + .width = 16, + }, +}; + +static const struct imx_cpi_plat_data imx8qxp_pdata = { + .version = PI_V1, + .if_ctrl_reg = 0x0, + .interface_status = 0x20, + .interface_ctrl_reg = 0x10, + .interface_ctrl_reg1 = 0x30, +}; + +static const struct imx_cpi_pix_format *find_imx_cpi_format(u32 code) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(imx_cpi_formats); i++) + if (code == imx_cpi_formats[i].code) + return &imx_cpi_formats[i]; + + return NULL; +} + +static void imx_cpi_sw_reset(struct imx_cpi_device *pcpidev) +{ + const struct imx_cpi_plat_data *pdata = pcpidev->pdata; + u32 val; + + /* Softwaret Reset */ + val = readl(pcpidev->regs + pdata->interface_ctrl_reg); + val |= CPI_CTRL_REG_SOFTRST; + writel(val, pcpidev->regs + pdata->interface_ctrl_reg); + + fsleep(500); + val = readl(pcpidev->regs + pdata->interface_ctrl_reg); + val &= ~CPI_CTRL_REG_SOFTRST; + writel(val, pcpidev->regs + pdata->interface_ctrl_reg); +} + +static void imx_cpi_hw_config(struct imx_cpi_device *pcpidev, + const struct imx_cpi_pix_format *pcpidev_fmt) +{ + const struct imx_cpi_plat_data *pdata = pcpidev->pdata; + u32 flags = pcpidev->sd_1to1.vep.bus.parallel.flags; + bool hsync_pol = flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH; + bool vsync_pol = flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH; + u32 val; + + /* Software Reset */ + imx_cpi_sw_reset(pcpidev); + + /* Config PL Data Type */ + val = IF_CTRL_REG_DATA_TYPE(DATA_TYPE_OUT_YUV444); + val |= IF_CTRL_REG_PL_ENABLE | IF_CTRL_REG_PL_VALID; + writel(val, pcpidev->regs + pdata->if_ctrl_reg); + + /* Config CTRL REG */ + val = CPI_CTRL_REG_HSYNC_FORCE_EN | CPI_CTRL_REG_VSYNC_FORCE_EN; + + val |= CPI_CTRL_REG_DATA_TYPE_IN(pcpidev_fmt->data_type) | + FIELD_PREP(CPI_CTRL_REG_HSYNC_POL, hsync_pol) | + FIELD_PREP(CPI_CTRL_REG_VSYNC_POL, vsync_pol) | + FIELD_PREP(CPI_CTRL_REG_PIXEL_CLK_POL, 0) | + CPI_CTRL_REG_MASK_VSYNC_COUNTER(3) | + CPI_CTRL_REG_HSYNC_PULSE(2); + + if (pcpidev_fmt->code == MEDIA_BUS_FMT_YUYV8_2X8 || + pcpidev_fmt->code == MEDIA_BUS_FMT_UYVY8_2X8) + val |= CPI_CTRL_REG_UV_SWAP_EN; + + if (pcpidev->mode == PI_GATE_CLOCK_MODE) { + val |= CPI_CTRL_REG_GCLK_MODE_EN; + } else if (pcpidev->mode == PI_CCIR_MODE) { + val |= (CPI_CTRL_REG_CCIR_EN | + CPI_CTRL_REG_CCIR_VSYNC_RESET_EN | + CPI_CTRL_REG_CCIR_EXT_VSYNC_EN | + CPI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN); + } + + writel(val, pcpidev->regs + pdata->interface_ctrl_reg); +} + +static void imx_cpi_config_ctrl_reg1(struct imx_cpi_device *pcpidev, + const struct v4l2_mbus_framefmt *format) +{ + const struct imx_cpi_plat_data *pdata = pcpidev->pdata; + u32 pixel_width; + u32 vsync_pulse; + u32 val; + + pixel_width = format->width - 1; + vsync_pulse = format->width << 1; + + switch (pcpidev->pdata->version) { + case PI_V1: + val = CPI_CTRL_REG1_PIXEL_WIDTH(pixel_width) | + CPI_CTRL_REG1_VSYNC_PULSE(vsync_pulse); + break; + default: + val = 0; /* Never happen */ + } + + val = CPI_CTRL_REG1_PIXEL_WIDTH(pixel_width) | + CPI_CTRL_REG1_VSYNC_PULSE(vsync_pulse); + writel(val, pcpidev->regs + pdata->interface_ctrl_reg1); +} + +static void imx_cpi_enable(struct imx_cpi_device *pcpidev) +{ + const struct imx_cpi_plat_data *pdata = pcpidev->pdata; + u32 val; + + /* Enable CPI */ + val = readl(pcpidev->regs + pdata->interface_ctrl_reg); + val |= CPI_CTRL_REG_CPI_EN; + writel(val, pcpidev->regs + pdata->interface_ctrl_reg); + + /* Disable SYNC Force */ + val = readl(pcpidev->regs + pdata->interface_ctrl_reg); + val &= ~(CPI_CTRL_REG_HSYNC_FORCE_EN | CPI_CTRL_REG_VSYNC_FORCE_EN); + writel(val, pcpidev->regs + pdata->interface_ctrl_reg); +} + +static void imx_cpi_disable(struct imx_cpi_device *pcpidev) +{ + const struct imx_cpi_plat_data *pdata = pcpidev->pdata; + u32 val; + + /* Enable Sync Force */ + val = readl(pcpidev->regs + pdata->interface_ctrl_reg); + val |= CPI_CTRL_REG_HSYNC_FORCE_EN | CPI_CTRL_REG_VSYNC_FORCE_EN; + writel(val, pcpidev->regs + pdata->interface_ctrl_reg); + + /* Disable CPI */ + val = readl(pcpidev->regs + pdata->interface_ctrl_reg); + val &= ~CPI_CTRL_REG_CPI_EN; + writel(val, pcpidev->regs + pdata->interface_ctrl_reg); + + /* Disable Pixel Link */ + val = readl(pcpidev->regs + pdata->if_ctrl_reg); + val &= ~(IF_CTRL_REG_PL_VALID | IF_CTRL_REG_PL_ENABLE); + writel(val, pcpidev->regs + pdata->if_ctrl_reg); +} + +static struct imx_cpi_device *sd_to_imx_cpi_device(struct v4l2_subdev *sdev) +{ + return container_of(sdev, struct imx_cpi_device, sd_1to1.sd); +} + +static const struct media_entity_operations imx_cpi_entity_ops = { + .link_validate = v4l2_subdev_link_validate, + .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1, +}; + +static int imx_cpi_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *sdformat) +{ + struct imx_cpi_pix_format const *pcpidev_fmt; + struct v4l2_mbus_framefmt *fmt; + + /* + * The Parallel cpi can't transcode in any way, the source format + * can't be modified. + */ + if (sdformat->pad == V4L2_SUBDEV_1TO1_PADS_SOURCE) + return v4l2_subdev_get_fmt(sd, sd_state, sdformat); + + pcpidev_fmt = find_imx_cpi_format(sdformat->format.code); + if (!pcpidev_fmt) + pcpidev_fmt = &imx_cpi_formats[0]; + + fmt = v4l2_subdev_state_get_format(sd_state, sdformat->pad); + + fmt->code = pcpidev_fmt->code; + fmt->width = sdformat->format.width; + fmt->height = sdformat->format.height; + fmt->field = V4L2_FIELD_NONE; + fmt->colorspace = sdformat->format.colorspace; + fmt->quantization = sdformat->format.quantization; + fmt->xfer_func = sdformat->format.xfer_func; + fmt->ycbcr_enc = sdformat->format.ycbcr_enc; + + sdformat->format = *fmt; + + /* Propagate the format from sink to source. */ + fmt = v4l2_subdev_state_get_format(sd_state, V4L2_SUBDEV_1TO1_PADS_SOURCE); + *fmt = sdformat->format; + + /* The format on the source pad might change due to unpacking. */ + fmt->code = pcpidev_fmt->output; + + return 0; +} + +static int imx_cpi_init_state(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state) +{ + struct v4l2_subdev_route routes[] = { + { + .sink_pad = V4L2_SUBDEV_1TO1_PADS_SINK, + .sink_stream = 0, + .source_pad = V4L2_SUBDEV_1TO1_PADS_SOURCE, + .source_stream = 0, + .flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE, + }, + }; + struct v4l2_subdev_krouting routing = { + .len_routes = ARRAY_SIZE(routes), + .num_routes = ARRAY_SIZE(routes), + .routes = routes, + }; + struct v4l2_mbus_framefmt *fmt; + + fmt = v4l2_subdev_state_get_format(state, 0); + + fmt->code = imx_cpi_formats[0].code; + fmt->width = 1920; + fmt->height = 1080; + + fmt->colorspace = V4L2_COLORSPACE_SMPTE170M; + fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace); + fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace); + fmt->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(false, + fmt->colorspace, + fmt->ycbcr_enc); + + return v4l2_subdev_set_routing_with_fmt(sd, state, &routing, fmt); +} + +static int imx_cpi_disable_streams(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, u32 pad, + u64 streams_mask) +{ + struct imx_cpi_device *pcpidev = sd_to_imx_cpi_device(sd); + struct media_pad *sink_pad, *remote_pad; + struct device *dev = pcpidev->dev; + struct v4l2_subdev *remote_sd; + u64 mask; + int ret; + + sink_pad = &sd->entity.pads[V4L2_SUBDEV_1TO1_PADS_SINK]; + remote_pad = media_pad_remote_pad_first(sink_pad); + remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity); + + mask = v4l2_subdev_state_xlate_streams(state, V4L2_SUBDEV_1TO1_PADS_SINK, + V4L2_SUBDEV_1TO1_PADS_SOURCE, + &streams_mask); + + ret = v4l2_subdev_disable_streams(remote_sd, remote_pad->index, mask); + if (ret) + dev_err(dev, "failed to disable streams on remote subdev: %d\n", ret); + + pcpidev->enabled_streams &= ~streams_mask; + + if (!pcpidev->enabled_streams) { + imx_cpi_disable(pcpidev); + pm_runtime_put_autosuspend(dev); + } + + return 0; +} + +static int imx_cpi_enable_streams(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, u32 pad, + u64 streams_mask) +{ + struct imx_cpi_device *pcpidev = sd_to_imx_cpi_device(sd); + const struct imx_cpi_pix_format *pcpidev_fmt; + const struct v4l2_mbus_framefmt *format; + struct media_pad *sink_pad, *remote_pad; + struct device *dev = pcpidev->dev; + struct v4l2_subdev *remote_sd; + u64 mask; + int ret; + + sink_pad = &sd->entity.pads[V4L2_SUBDEV_1TO1_PADS_SINK]; + remote_pad = media_pad_remote_pad_first(sink_pad); + remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity); + + mask = v4l2_subdev_state_xlate_streams(state, V4L2_SUBDEV_1TO1_PADS_SINK, + V4L2_SUBDEV_1TO1_PADS_SOURCE, + &streams_mask); + + format = v4l2_subdev_state_get_format(state, V4L2_SUBDEV_1TO1_PADS_SINK); + pcpidev_fmt = find_imx_cpi_format(format->code); + + if (!pcpidev->enabled_streams) { + ret = pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + imx_cpi_hw_config(pcpidev, pcpidev_fmt); + imx_cpi_config_ctrl_reg1(pcpidev, format); + imx_cpi_enable(pcpidev); + } + + ret = v4l2_subdev_enable_streams(remote_sd, remote_pad->index, mask); + if (ret) + goto err_cpi_stop; + + pcpidev->enabled_streams |= streams_mask; + + return 0; + +err_cpi_stop: + /* Stop CSI hardware if no streams are enabled */ + if (!pcpidev->enabled_streams) + imx_cpi_disable(pcpidev); + + pm_runtime_put_autosuspend(dev); + + return ret; +} + +static int imx_cpi_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + /* + * The PARALLEL CPI can't transcode in any way, the source format + * is identical to the sink format. + */ + if (code->pad == V4L2_SUBDEV_1TO1_PADS_SOURCE) { + struct v4l2_mbus_framefmt *fmt; + + if (code->index > 0) + return -EINVAL; + + fmt = v4l2_subdev_state_get_format(sd_state, code->pad); + code->code = fmt->code; + return 0; + } + + if (code->pad != V4L2_SUBDEV_1TO1_PADS_SINK) + return -EINVAL; + + if (code->index >= ARRAY_SIZE(imx_cpi_formats)) + return -EINVAL; + + code->code = imx_cpi_formats[code->index].code; + + return 0; +} + +static const struct v4l2_subdev_video_ops imx_cpi_video_ops = { + .s_stream = v4l2_subdev_s_stream_helper, +}; + +static const struct v4l2_subdev_pad_ops imx_cpi_pad_ops = { + .enum_mbus_code = imx_cpi_enum_mbus_code, + .get_fmt = v4l2_subdev_get_fmt, + .set_fmt = imx_cpi_set_fmt, + .get_frame_desc = v4l2_subdev_get_frame_desc_passthrough, + .enable_streams = imx_cpi_enable_streams, + .disable_streams = imx_cpi_disable_streams, +}; + +static const struct v4l2_subdev_ops imx_cpi_subdev_ops = { + .pad = &imx_cpi_pad_ops, + .video = &imx_cpi_video_ops, +}; + +static const struct v4l2_subdev_internal_ops imx_cpi_internal_ops = { + .init_state = imx_cpi_init_state, +}; + +/* ---------------------------------------------------------------------- + * Suspend/resume + */ + +static int imx_cpi_runtime_suspend(struct device *dev) +{ + struct imx_cpi_device *pcpidev = dev_get_drvdata(dev); + + clk_bulk_disable_unprepare(pcpidev->num_clks, pcpidev->clks); + + return 0; +} + +static int imx_cpi_runtime_resume(struct device *dev) +{ + struct imx_cpi_device *pcpidev = dev_get_drvdata(dev); + + return clk_bulk_prepare_enable(pcpidev->num_clks, pcpidev->clks); +} + +static const struct dev_pm_ops imx_cpi_pm_ops = { + RUNTIME_PM_OPS(imx_cpi_runtime_suspend, imx_cpi_runtime_resume, NULL) +}; + +static void imx_cpi_remove(struct platform_device *pdev) +{ + struct imx_cpi_device *pcpidev = platform_get_drvdata(pdev); + + media_async_subdev_1to1_cleanup(&pcpidev->sd_1to1); +} + +static int imx_cpi_probe(struct platform_device *pdev) +{ + struct imx_cpi_device *pcpidev; + struct device *dev = &pdev->dev; + struct v4l2_subdev *sd; + int ret; + + pcpidev = devm_kzalloc(dev, sizeof(*pcpidev), GFP_KERNEL); + if (!pcpidev) + return -ENOMEM; + + pcpidev->dev = dev; + platform_set_drvdata(pdev, pcpidev); + + pcpidev->pdata = of_device_get_match_data(dev); + pcpidev->mode = PI_GATE_CLOCK_MODE; + + pcpidev->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pcpidev->regs)) + return dev_err_probe(dev, PTR_ERR(pcpidev->regs), + "Failed to get regs\n"); + + pcpidev->num_clks = devm_clk_bulk_get_all(dev, &pcpidev->clks); + if (pcpidev->num_clks < 0) + return pcpidev->num_clks; + + sd = &pcpidev->sd_1to1.sd; + + v4l2_subdev_init(sd, &imx_cpi_subdev_ops); + + sd->internal_ops = &imx_cpi_internal_ops; + snprintf(sd->name, sizeof(sd->name), "parallel-%s", + dev_name(pcpidev->dev)); + + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + + sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; + sd->entity.ops = &imx_cpi_entity_ops; + + sd->dev = pcpidev->dev; + pcpidev->sd_1to1.remote_bustype_cap_mask = BIT(V4L2_MBUS_PARALLEL); + + pm_runtime_use_autosuspend(dev); + ret = devm_pm_runtime_enable(dev); + if (ret) + return ret; + + return media_async_register_subdev_1to1(&pcpidev->sd_1to1); +} + +static const struct of_device_id imx_cpi_of_match[] = { + { .compatible = "fsl,imx8qxp-pcif", .data = &imx8qxp_pdata }, + { }, +}; + +MODULE_DEVICE_TABLE(of, imx_cpi_of_match); + +static struct platform_driver imx_cpi_driver = { + .probe = imx_cpi_probe, + .remove = imx_cpi_remove, + .driver = { + .of_match_table = imx_cpi_of_match, + .name = "imx-parallel-cpi", + .pm = pm_ptr(&imx_cpi_pm_ops), + }, +}; + +module_platform_driver(imx_cpi_driver); + +MODULE_DESCRIPTION("i.MX9 Parallel CPI receiver driver"); +MODULE_LICENSE("GPL"); -- 2.43.0