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Signed-off-by: Frank Li --- changes in v4 - add hsync-active = <1> changes in v3 - replace csi with cpi. - use imx8qxp-mek-ov5640-cpi.dtso since csi use imx8qxp-mek-ov5640-csi.dtso change in v2 - move ov5640 part to overlay file - rename to imx8qxp-mek-ov5640-parallel.dtso - remove data-lanes --- arch/arm64/boot/dts/freescale/Makefile | 3 + .../boot/dts/freescale/imx8qxp-mek-ov5640-cpi.dtso | 83 ++++++++++++++++++++++ 2 files changed, 86 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 001ca3a12c0ae..3b9e9844f11ef 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -554,6 +554,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-pcie-ep.dtb imx8qxp-mek-ov5640-csi-dtbs := imx8qxp-mek.dtb imx8qxp-mek-ov5640-csi.dtbo dtb-${CONFIG_ARCH_MXC} += imx8qxp-mek-ov5640-csi.dtb +imx8qxp-mek-ov5640-cpi-dtbs := imx8qxp-mek.dtb imx8qxp-mek-ov5640-cpi.dtbo +dtb-${CONFIG_ARCH_MXC} += imx8qxp-mek-ov5640-cpi.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-cpi.dtso b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-cpi.dtso new file mode 100644 index 0000000000000..9fbdd798f17d6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-cpi.dtso @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +&cm40_i2c { + #address-cells = <1>; + #size-cells = <0>; + + ov5640_pi: camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + clocks = <&pi0_misc_lpcg IMX_LPCG_CLK_0>; + clock-names = "xclk"; + assigned-clocks = <&pi0_misc_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <24000000>; + AVDD-supply = <®_2v8>; + DOVDD-supply = <®_1v8>; + DVDD-supply = <®_1v5>; + pinctrl-0 = <&pinctrl_parallel_cpi>; + pinctrl-names = "default"; + powerdown-gpios = <&lsio_gpio3 2 GPIO_ACTIVE_HIGH>; + reset-gpios = <&lsio_gpio3 3 GPIO_ACTIVE_LOW>; + + port { + ov5640_pi_ep: endpoint { + bus-type = ; + bus-width = <8>; + hsync-active = <1>; + pclk-sample = <1>; + remote-endpoint = <¶llel_cpi_in>; + vsync-active = <0>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_parallel_cpi: parallelcpigrp { + fsl,pins = < + IMX8QXP_CSI_D00_CI_PI_D02 0xc0000041 + IMX8QXP_CSI_D01_CI_PI_D03 0xc0000041 + IMX8QXP_CSI_D02_CI_PI_D04 0xc0000041 + IMX8QXP_CSI_D03_CI_PI_D05 0xc0000041 + IMX8QXP_CSI_D04_CI_PI_D06 0xc0000041 + IMX8QXP_CSI_D05_CI_PI_D07 0xc0000041 + IMX8QXP_CSI_D06_CI_PI_D08 0xc0000041 + IMX8QXP_CSI_D07_CI_PI_D09 0xc0000041 + + IMX8QXP_CSI_MCLK_CI_PI_MCLK 0xc0000041 + IMX8QXP_CSI_PCLK_CI_PI_PCLK 0xc0000041 + IMX8QXP_CSI_HSYNC_CI_PI_HSYNC 0xc0000041 + IMX8QXP_CSI_VSYNC_CI_PI_VSYNC 0xc0000041 + IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0xc0000041 + IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0xc0000041 + >; + }; +}; + +&isi { + status = "okay"; +}; + +¶llel_cpi { + status = "okay"; + + ports { + port@0 { + parallel_cpi_in: endpoint { + hsync-active = <1>; + remote-endpoint = <&ov5640_pi_ep>; + }; + }; + }; +}; -- 2.43.0