Re: [PATCH v2 1/2] dt-bindings: clock: ultrarisc: Add DP1000 Clock Controller

[Conor Dooley <conor@kernel.org>]

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On Wed, Jun 17, 2026 at 02:02:54PM +0800, Jia Wang via B4 Relay wrote:
> From: Jia Wang <wangjia@ultrarisc.com>
> 
> Add doc for the clock controller on the UltraRISC DP1000 RISC-V SoC.
> 
> Signed-off-by: Jia Wang <wangjia@ultrarisc.com>

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

Cheers,
Conor.

> ---
>  .../bindings/clock/ultrarisc,dp1000-clk.yaml       | 60 ++++++++++++++++++++++
>  MAINTAINERS                                        |  7 +++
>  include/dt-bindings/clock/ultrarisc,dp1000-clk.h   | 27 ++++++++++
>  3 files changed, 94 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/ultrarisc,dp1000-clk.yaml b/Documentation/devicetree/bindings/clock/ultrarisc,dp1000-clk.yaml
> new file mode 100644
> index 000000000000..ede565ec440c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/ultrarisc,dp1000-clk.yaml
> @@ -0,0 +1,60 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/ultrarisc,dp1000-clk.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: UltraRISC DP1000 Clock Controller
> +
> +maintainers:
> +  - Jia Wang <wangjia@ultrarisc.com>
> +
> +description: |
> +  The UltraRISC DP1000 clock controller is driven from a single external
> +  oscillator input. It provides a system PLL with fractional multiplier
> +  and post-divider stages, several fixed-ratio derived clocks for
> +  the on-chip subsystem, Clock Configuration Register (CCR) divider
> +  outputs for GMAC and the UART, I2C, and SPI root clocks, and
> +  per-instance gate clocks for UART0-3, I2C0-3, and SPI0-1.
> +
> +  All available clocks are defined as preprocessor macros in
> +  include/dt-bindings/clock/ultrarisc,dp1000-clk.h
> +
> +properties:
> +  compatible:
> +    const: ultrarisc,dp1000-clk
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +    description:
> +      External oscillator input clock used as the parent of the PLLs.
> +
> +  "#clock-cells":
> +    const: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - "#clock-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/ultrarisc,dp1000-clk.h>
> +
> +    soc {
> +      #address-cells = <2>;
> +      #size-cells = <2>;
> +
> +      clock-controller@11080000 {
> +        compatible = "ultrarisc,dp1000-clk";
> +        reg = <0x0 0x11080000 0x0 0x1000>;
> +        clocks = <&osc>;
> +        #clock-cells = <1>;
> +      };
> +    };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 3d6db8cb608f..b7e43313c65f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -27439,6 +27439,13 @@ S:	Maintained
>  F:	drivers/usb/common/ulpi.c
>  F:	include/linux/ulpi/
>  
> +ULTRARISC DP1000 CLOCK DRIVER
> +M:	Jia Wang <wangjia@ultrarisc.com>
> +L:	linux-clk@vger.kernel.org
> +S:	Maintained
> +F:	Documentation/devicetree/bindings/clock/ultrarisc,dp1000-clk.yaml
> +F:	include/dt-bindings/clock/ultrarisc,dp1000-clk.h
> +
>  ULTRATRONIK BOARD SUPPORT
>  M:	Goran Rađenović <goran.radni@gmail.com>
>  M:	Börge Strümpfel <boerge.struempfel@gmail.com>
> diff --git a/include/dt-bindings/clock/ultrarisc,dp1000-clk.h b/include/dt-bindings/clock/ultrarisc,dp1000-clk.h
> new file mode 100644
> index 000000000000..751125f99965
> --- /dev/null
> +++ b/include/dt-bindings/clock/ultrarisc,dp1000-clk.h
> @@ -0,0 +1,27 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +#ifndef _DT_BINDINGS_CLOCK_ULTRARISC_DP1000_CLK_H
> +#define _DT_BINDINGS_CLOCK_ULTRARISC_DP1000_CLK_H
> +
> +#define DP1000_CLK_SYSPLL		0
> +#define DP1000_CLK_SYSPLL_DIV2		1
> +#define DP1000_CLK_SUBSYS		2
> +#define DP1000_CLK_GMAC			3
> +#define DP1000_CLK_UART_ROOT		4
> +#define DP1000_CLK_I2C_ROOT		5
> +#define DP1000_CLK_SPI_ROOT		6
> +#define DP1000_CLK_PCIE_DBI		7
> +#define DP1000_CLK_PCIEX4_CORE		8
> +#define DP1000_CLK_PCIEX16_CORE		9
> +#define DP1000_CLK_PCIE_AUX		10
> +#define DP1000_CLK_UART0		11
> +#define DP1000_CLK_UART1		12
> +#define DP1000_CLK_UART2		13
> +#define DP1000_CLK_UART3		14
> +#define DP1000_CLK_I2C0			15
> +#define DP1000_CLK_I2C1			16
> +#define DP1000_CLK_I2C2			17
> +#define DP1000_CLK_I2C3			18
> +#define DP1000_CLK_SPI0			19
> +#define DP1000_CLK_SPI1			20
> +
> +#endif /* _DT_BINDINGS_CLOCK_ULTRARISC_DP1000_CLK_H */
> 
> -- 
> 2.34.1
> 
> 
> 

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