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Thu, 18 Jun 2026 05:02:03 -0700 (PDT) From: Jad Keskes To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivia Mackall , Herbert Xu Cc: Alexander Clouter , devicetree@vger.kernel.org, linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, Jad Keskes Subject: [PATCH v5 2/2] hw_random: timeriomem-rng: add configurable read width and data mask Date: Thu, 18 Jun 2026 13:01:10 +0100 Message-ID: <20260618120110.36439-2-inasj268@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260618120110.36439-1-inasj268@gmail.com> References: <20260618120110.36439-1-inasj268@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The TODO for supporting read sizes other than 32 bits and masking has been sitting in this driver since 2009. Implement it. Add reg-io-width (1, 2, or 4 bytes) and mask support. The read loop dispatches on width using readb/readw/readl so a configured 1-byte access does not trigger a bus error on hardware that rejects 32-bit reads to that address. The mask is ANDed with the value before storing. These are platform properties, not runtime policy -- width depends on SoC integration, mask reflects which output bits carry entropy. The alignment check in probe is updated to verify the resource is aligned to the configured width instead of hardcoding 4-byte alignment. Signed-off-by: Jad Keskes --- v5: No changes since v4 v4: Initial version with reg-io-width (bytes) and readb/readw/readl v3: Added configurable width (bits) with mask v2: Rebased v1: Initial submission --- drivers/char/hw_random/timeriomem-rng.c | 77 ++++++++++++++++++++----- include/linux/timeriomem-rng.h | 12 ++++ 2 files changed, 76 insertions(+), 13 deletions(-) diff --git a/drivers/char/hw_random/timeriomem-rng.c b/drivers/char/hw_random/timeriomem-rng.c index e61f06393209..42393409f22a 100644 --- a/drivers/char/hw_random/timeriomem-rng.c +++ b/drivers/char/hw_random/timeriomem-rng.c @@ -14,7 +14,9 @@ * has to do is provide the address and 'wait time' that new data becomes * available. * - * TODO: add support for reading sizes other than 32bits and masking + * The read width (8, 16, or 32 bits) and an optional data mask can be + * configured through platform data or device tree properties. Default is + * 32-bit reads with no mask. */ #include @@ -34,6 +36,8 @@ struct timeriomem_rng_private { void __iomem *io_base; ktime_t period; unsigned int present:1; + unsigned int reg_io_width; + u32 mask; struct hrtimer timer; struct completion completion; @@ -48,6 +52,7 @@ static int timeriomem_rng_read(struct hwrng *hwrng, void *data, container_of(hwrng, struct timeriomem_rng_private, rng_ops); int retval = 0; int period_us = ktime_to_us(priv->period); + int chunk = priv->reg_io_width; /* * There may not have been enough time for new data to be generated @@ -71,11 +76,28 @@ static int timeriomem_rng_read(struct hwrng *hwrng, void *data, usleep_range(period_us, period_us + max(1, period_us / 100)); - *(u32 *)data = readl(priv->io_base); - retval += sizeof(u32); - data += sizeof(u32); - max -= sizeof(u32); - } while (wait && max > sizeof(u32)); + switch (priv->reg_io_width) { + case 1: { + u8 val = readb(priv->io_base) & priv->mask; + *(u8 *)data = val; + break; + } + case 2: { + u16 val = readw(priv->io_base) & priv->mask; + *(u16 *)data = val; + break; + } + case 4: { + u32 val = readl(priv->io_base) & priv->mask; + *(u32 *)data = val; + break; + } + } + + retval += chunk; + data += chunk; + max -= chunk; + } while (wait && max > chunk); /* * Block any new callers until the RNG has had time to generate new @@ -125,11 +147,8 @@ static int timeriomem_rng_probe(struct platform_device *pdev) if (IS_ERR(priv->io_base)) return PTR_ERR(priv->io_base); - if (res->start % 4 != 0 || resource_size(res) < 4) { - dev_err(&pdev->dev, - "address must be at least four bytes wide and 32-bit aligned\n"); - return -EINVAL; - } + priv->reg_io_width = 4; + priv->mask = 0xFFFFFFFF; if (pdev->dev.of_node) { int i; @@ -145,9 +164,41 @@ static int timeriomem_rng_probe(struct platform_device *pdev) if (!of_property_read_u32(pdev->dev.of_node, "quality", &i)) priv->rng_ops.quality = i; + + of_property_read_u32(pdev->dev.of_node, + "reg-io-width", &priv->reg_io_width); + of_property_read_u32(pdev->dev.of_node, + "mask", &priv->mask); } else { period = pdata->period; priv->rng_ops.quality = pdata->quality; + + if (pdata->reg_io_width_set) + priv->reg_io_width = pdata->reg_io_width; + if (pdata->mask_set) + priv->mask = pdata->mask; + } + + if (priv->reg_io_width == 0) + priv->reg_io_width = 4; + + switch (priv->reg_io_width) { + case 1: + case 2: + case 4: + break; + default: + dev_err(&pdev->dev, "invalid reg-io-width %u, must be 1, 2, or 4\n", + priv->reg_io_width); + return -EINVAL; + } + + if (!IS_ALIGNED(res->start, priv->reg_io_width) || + resource_size(res) < priv->reg_io_width) { + dev_err(&pdev->dev, + "address must be %u-byte aligned\n", + priv->reg_io_width); + return -EINVAL; } priv->period = us_to_ktime(period); @@ -167,8 +218,8 @@ static int timeriomem_rng_probe(struct platform_device *pdev) return err; } - dev_info(&pdev->dev, "32bits from 0x%p @ %dus\n", - priv->io_base, period); + dev_info(&pdev->dev, "%u-byte from %p @ %dus\n", + priv->reg_io_width, priv->io_base, period); return 0; } diff --git a/include/linux/timeriomem-rng.h b/include/linux/timeriomem-rng.h index 672df7fbf6c1..5732489a17a1 100644 --- a/include/linux/timeriomem-rng.h +++ b/include/linux/timeriomem-rng.h @@ -16,6 +16,18 @@ struct timeriomem_rng_data { /* bits of entropy per 1024 bits read */ unsigned int quality; + + /* read width (1, 2, or 4 bytes), 0 means 4 */ + unsigned int reg_io_width; + + /* set to true if reg-io-width is explicitly provided */ + bool reg_io_width_set; + + /* mask applied to raw read value */ + u32 mask; + + /* set to true if mask is explicitly provided */ + bool mask_set; }; #endif /* _LINUX_TIMERIOMEM_RNG_H */ -- 2.54.0