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Sun, 21 Jun 2026 03:08:50 -0700 (PDT) Received: from claudeLX-01.hammies.cc ([165.173.24.245]) by smtp.gmail.com with ESMTPSA id af79cd13be357-921db359a7csm545405085a.38.2026.06.21.03.08.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2026 03:08:49 -0700 (PDT) From: Alvin Lim To: linux-ide@vger.kernel.org Cc: Damien Le Moal , Niklas Cassel , linux-kernel@vger.kernel.org, Alvin Lim , stable@vger.kernel.org Subject: [PATCH] ata: ahci: force 32-bit DMA for ASMedia ASM1166 Date: Sun, 21 Jun 2026 18:08:44 +0800 Message-ID: <20260621100844.1224301-1-alvinwylim@gmail.com> X-Mailer: git-send-email 2.47.3 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The ASMedia ASM1166 SATA controller (1b21:1166) advertises 64-bit DMA support (AHCI CAP.S64A), but on systems with the IOMMU enabled - where it can be handed DMA addresses above 4 GB - it silently corrupts data in transit. Reads return different, wrong data on each access. SMART is clean, there are no SATA link resets and no MCE is raised, so the corruption is invisible until it surfaces as filesystem metadata errors (XFS EUCLEAN) or, on Ceph, mass scrub errors across multiple independent filesystems at once - i.e. host-level, not filesystem-level. This is the same failure mode already quirked for other controllers that falsely claim working 64-bit DMA. See commit 105c42566a55 ("ata: ahci: force 32-bit DMA for JMicron JMB582/JMB585") and commit 20730e9b2778 ("ahci: add 43-bit DMA address quirk for ASMedia ASM1061 controllers"). The ASM1166 currently maps to plain board_ahci with no DMA limit. Limit the ASM1166 to 32-bit DMA. 32-bit is the guaranteed-correct lower bound; the only cost is extra SWIOTLB bounce-buffering on transfers above 4 GB, negligible for storage. A future change can widen it to the controller's true addressable width if characterised. Until this lands the only workarounds are disabling the IOMMU (amd_iommu=off / intel_iommu=off) or using an HBA. Reproduced on an AOOSTAR WTR MAX (AMD Ryzen 7 PRO 8845HS) whose six SATA bays all hang off one ASM1166: with the IOMMU on, six concurrent 'dd ... | md5sum' of the same large file return six different sums; with amd_iommu=off they are identical, and a full Ceph deep-scrub of a 5.4 TiB / 1.43M-object pool re-reads end-to-end with zero scrub errors. Add a board_ahci_32bit_dma board type (mirroring board_ahci_43bit_dma) and point the ASM1166 entry at it. Fixes: 3bf614106094 ("ata: ahci: add identifiers for ASM2116 series adapters") Cc: stable@vger.kernel.org Assisted-by: Claude:claude-opus-4.8 Signed-off-by: Alvin Lim --- drivers/ata/ahci.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 58f512f8952a..895956c2ca15 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -48,6 +48,7 @@ enum { enum board_ids { /* board IDs by feature in alphabetical order */ board_ahci, + board_ahci_32bit_dma, board_ahci_43bit_dma, board_ahci_ign_iferr, board_ahci_no_debounce_delay, @@ -132,6 +133,13 @@ static const struct ata_port_info ahci_port_info[] = { .udma_mask = ATA_UDMA6, .port_ops = &ahci_ops, }, + [board_ahci_32bit_dma] = { + AHCI_HFLAGS (AHCI_HFLAG_32BIT_ONLY), + .flags = AHCI_FLAG_COMMON, + .pio_mask = ATA_PIO4, + .udma_mask = ATA_UDMA6, + .port_ops = &ahci_ops, + }, [board_ahci_43bit_dma] = { AHCI_HFLAGS (AHCI_HFLAG_43BIT_ONLY), .flags = AHCI_FLAG_COMMON, @@ -1559,7 +1567,7 @@ static const struct pci_device_id ahci_pci_tbl[] = { }, { /* ASM1166 */ PCI_VDEVICE(ASMEDIA, 0x1166), - .driver_data = board_ahci, + .driver_data = board_ahci_32bit_dma, }, { /* * Samsung SSDs found on some macbooks. NCQ times out if MSI is base-commit: 322008f87f917e2217eeac386a9410945092eb2e -- 2.47.3