From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-181.mta0.migadu.com (out-181.mta0.migadu.com [91.218.175.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4A7938F240 for ; Mon, 22 Jun 2026 08:05:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.181 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782115558; cv=none; b=Y6IEJRRVaO01hHExQ5CZPMPHzFoy0Srf2a9vMK+q9OL8TP2Duo676B5E4e3we15x9CtXAMXweOW2Da9OLAjJSxKe7H/0wp4jp339J/fbVDTKbL3ZZjH1UJrldWdpWOO3UDoE4Ab/o7xvGe9XVihY7Boj/qJ9XAGGKwn8aFFEk7o= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782115558; c=relaxed/simple; bh=fm/4rOuaf5s4k9gv3Kh4y/TD15tN7Ll4EJ02OknVvP4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aG4z+82C8AFICt+Qf2ZYrkXx0V7DCczhoOBIe4rYG2qjHcm+ywfrjdvWqARfxKiThYxrkASRVzWad3x5V9AoLM4WMbgUL6/RO9qeV0fh4dYbU9dwRMBLqdlaWx2FooeEXTz7fQvGN19Q+E8KacM0vZXgY5jtSI2qxZfh4GYdmBs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=g3DDdUKe; arc=none smtp.client-ip=91.218.175.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="g3DDdUKe" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782115554; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=t5WWYP56pCGTz4m0LRXwiLCCNwfMiyvtrU+b3gWyvX4=; b=g3DDdUKedJ6NuSyJwzHAvZHXhzYeka92zNPAPHkRqCv4kFapHyqmsLXthA5dp9+eP9Ie4F V5rqqboNmpAk2PmBVVeV+kqGkIxpWA/RiPyovoEuPrl83Gl+0+yXb8WYTGhPNHmdhI5itq Sd3mOUHhyd6DyEJ1mTNJLzrZ44Zb2Gk= From: Atish Patra Date: Mon, 22 Jun 2026 01:04:25 -0700 Subject: [PATCH v7 13/22] RISC-V: perf: Add a mechanism to defined legacy event encoding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260622-counter_delegation-v7-13-0ba2fd34614e@meta.com> References: <20260622-counter_delegation-v7-0-0ba2fd34614e@meta.com> In-Reply-To: <20260622-counter_delegation-v7-0-0ba2fd34614e@meta.com> To: Jiri Olsa , James Clark , Mark Rutland , Will Deacon , Arnaldo Carvalho de Melo , Rob Herring , Ian Rogers , Krzysztof Kozlowski , Anup Patel , Paul Walmsley , Atish Patra , Namhyung Kim Cc: devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org X-Migadu-Flow: FLOW_OUT From: Atish Patra RISC-V ISA doesn't define any standard event encodings or specify any event to counter mapping. Thus, event encoding information and corresponding counter mapping fot those events needs to be provided in the driver for each vendor. Add a framework to support that. The individual platform events will be added later. Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 70 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 69 insertions(+), 1 deletion(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index d44f47613aa1..1c0961e09b15 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -10,6 +10,7 @@ #define pr_fmt(fmt) "riscv-pmu-sbi: " fmt +#include #include #include #include @@ -379,6 +380,71 @@ static int pmu_sbi_check_event_info(void) return result; } +/* + * Vendor specific PMU events. + */ +struct riscv_pmu_event { + u64 event_id; + u32 counter_mask; +}; + +#define HW_OP_UNSUPPORTED U64_MAX +#define CACHE_OP_UNSUPPORTED U64_MAX + +#define PERF_MAP_ALL_UNSUPPORTED \ + [0 ... PERF_COUNT_HW_MAX - 1] = {HW_OP_UNSUPPORTED, 0x0} + +#define PERF_CACHE_MAP_ALL_UNSUPPORTED \ +[0 ... PERF_COUNT_HW_CACHE_MAX - 1] = { \ + [0 ... PERF_COUNT_HW_CACHE_OP_MAX - 1] = { \ + [0 ... PERF_COUNT_HW_CACHE_RESULT_MAX - 1] = { \ + CACHE_OP_UNSUPPORTED, 0x0 \ + }, \ + }, \ +} + +struct riscv_vendor_pmu_events { + unsigned long vendorid; + unsigned long archid; + unsigned long implid; + const struct riscv_pmu_event *hw_event_map; + const struct riscv_pmu_event (*cache_event_map)[PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX]; +}; + +#define RISCV_VENDOR_PMU_EVENTS(_vendorid, _archid, _implid, _hw_event_map, _cache_event_map) \ + { .vendorid = _vendorid, .archid = _archid, .implid = _implid, \ + .hw_event_map = _hw_event_map, .cache_event_map = _cache_event_map }, + +static struct riscv_vendor_pmu_events pmu_vendor_events_table[] = { +}; + +static const struct riscv_pmu_event *current_pmu_hw_event_map; +static const struct riscv_pmu_event (*current_pmu_cache_event_map)[PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX]; + +static void __init rvpmu_vendor_register_events(void) +{ + int cpu = raw_smp_processor_id(); + unsigned long vendor_id = riscv_cached_mvendorid(cpu); + unsigned long impl_id = riscv_cached_mimpid(cpu); + unsigned long arch_id = riscv_cached_marchid(cpu); + + for (int i = 0; i < ARRAY_SIZE(pmu_vendor_events_table); i++) { + if (pmu_vendor_events_table[i].vendorid == vendor_id && + pmu_vendor_events_table[i].implid == impl_id && + pmu_vendor_events_table[i].archid == arch_id) { + current_pmu_hw_event_map = pmu_vendor_events_table[i].hw_event_map; + current_pmu_cache_event_map = pmu_vendor_events_table[i].cache_event_map; + break; + } + } + + if (!current_pmu_hw_event_map || !current_pmu_cache_event_map) { + pr_info("No default PMU events found\n"); + } +} + static void rvpmu_sbi_check_event(struct sbi_pmu_event_data *edata) { struct sbiret ret; @@ -1660,8 +1726,10 @@ static int __init rvpmu_devinit(void) */ if (riscv_isa_extension_available(NULL, SSCCFG) && riscv_isa_extension_available(NULL, SMCDELEG) && - riscv_isa_extension_available(NULL, SSCSRIND)) + riscv_isa_extension_available(NULL, SSCSRIND)) { static_branch_enable(&riscv_pmu_cdeleg_available); + rvpmu_vendor_register_events(); + } if (!(riscv_pmu_sbi_available_boot() || riscv_pmu_cdeleg_available_boot())) return 0; -- 2.53.0-Meta