From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-170.mta0.migadu.com (out-170.mta0.migadu.com [91.218.175.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55C9939280D for ; Mon, 22 Jun 2026 08:06:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.170 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782115589; cv=none; b=otjoIaBv8NC7WwtY6Vksa5fZcsfctY+R0iX4WHYlQI6w1nfihH6yxM52DZYsLmX1ATZ2REH70yX5Y7BHLxLuvMDRusEkOPgmSYZuaAXSyXtnarwgq+2tStMk2umQh/punOt2XzHd2Y5YC/0kThdvezTTjqw39pvUhj2RI/W3Ows= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782115589; c=relaxed/simple; bh=tcAXakJhKBjuvVmb0v78jyS6JLvU0CzySqdkDuRpiVs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kJS1oywjE5KtXiTedfXdVlu1yvgxkf6NztSVLLwIStPqYB0xMzoDGEZA7sbihMJXJmzcKGuGVnRvdhQqp1idhrqB40WG9eOxyvHBtpsCNZVb0cp7cpPi2lTRR0qntOATo/bVSNfPzrCnG6tw8c0/Lu+M01A9NhkTbsXBmPytv2k= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=Hz/AlxmS; arc=none smtp.client-ip=91.218.175.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="Hz/AlxmS" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782115586; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Ea3qX/iYYZe37EiflUkHEkxWKDcUhucpAlxGsriXrfg=; b=Hz/AlxmSGVIw0yDaoAbncHQlZ7hUowxBQwkuMTYRirIjCBNMb9z1F/Q1xxFBdKCOqLuYjJ DcYtk2AgYoeOWDe/gtYsHA73EvHtop1BYaFpFuzlfZFn4FxjHAZkpeBLiVY1XxgzEaxQHF feabxqsUeBSUaiJ60IYECmWHEjsy/io= From: Atish Patra Date: Mon, 22 Jun 2026 01:04:33 -0700 Subject: [PATCH v7 21/22] TEST(do-not-upstream): fake qemu-virt PMU events for cdeleg counter-mask testing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260622-counter_delegation-v7-21-0ba2fd34614e@meta.com> References: <20260622-counter_delegation-v7-0-0ba2fd34614e@meta.com> In-Reply-To: <20260622-counter_delegation-v7-0-0ba2fd34614e@meta.com> To: Jiri Olsa , James Clark , Mark Rutland , Will Deacon , Arnaldo Carvalho de Melo , Rob Herring , Ian Rogers , Krzysztof Kozlowski , Anup Patel , Paul Walmsley , Atish Patra , Namhyung Kim Cc: devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org X-Migadu-Flow: FLOW_OUT From: Atish Patra Adds fake-any/fake-ctr3/fake-ctr34 (event codes 0xF0x QEMU doesn't model) with counterid_masks, to exercise the counter-delegation allocation + counter-mask constraint in QEMU (events read 0 = allocated/programmed, vs 'not supported'). Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 3cb7a1f4035e..13a9f1fe4293 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -492,6 +492,12 @@ RVPMU_EVENT_CMASK_ATTR(instructions, instructions, 0x02, 0xFFFFFFF8); RVPMU_EVENT_CMASK_ATTR(dTLB-load-misses, dTLB_load_miss, 0x10019, 0xFFFFFFF8); RVPMU_EVENT_CMASK_ATTR(dTLB-store-misses, dTLB_store_miss, 0x1001B, 0xFFFFFFF8); RVPMU_EVENT_CMASK_ATTR(iTLB-load-misses, iTLB_load_miss, 0x10021, 0xFFFFFFF8); +/* + * FAKE events for cdeleg mechanism testing: event codes QEMU does NOT model. + */ +RVPMU_EVENT_CMASK_ATTR(fake-any, fake_any, 0xF00, 0xFFFFFFF8); +RVPMU_EVENT_CMASK_ATTR(fake-ctr3, fake_ctr3, 0xF01, 0x8); +RVPMU_EVENT_CMASK_ATTR(fake-ctr34, fake_ctr34, 0xF02, 0x18); static struct attribute *qemu_virt_event_group[] = { RVPMU_EVENT_ATTR_PTR(cycles), @@ -499,6 +505,9 @@ static struct attribute *qemu_virt_event_group[] = { RVPMU_EVENT_ATTR_PTR(dTLB_load_miss), RVPMU_EVENT_ATTR_PTR(dTLB_store_miss), RVPMU_EVENT_ATTR_PTR(iTLB_load_miss), + RVPMU_EVENT_ATTR_PTR(fake_any), + RVPMU_EVENT_ATTR_PTR(fake_ctr3), + RVPMU_EVENT_ATTR_PTR(fake_ctr34), NULL, }; -- 2.53.0-Meta