From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C1E02DB7BE for ; Mon, 22 Jun 2026 11:48:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782128890; cv=none; b=QvoJOh4t7FG3iWNC1LJK00AsPNeM8VYBYoYFrmGPUr6fUD5MNg4JKgnJ3D/+p1QwP0n73J19q0eC8t3jsmISel19jvmo7GQ5v70yP3qK+SAU11ih9rOde6y8vn83G4LFCgCFnRqZmGKAH/ESezDe/sbeygbl9Pi15Qvgn44b+VA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782128890; c=relaxed/simple; bh=JJl24Emz4h3SZMr+NKGGApmvGaEAa8iddIdzOoS2KrE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MYyDlrcVDqpyjskEbW2p1ISTgXNzXTNmq2O9SUh+anHTCa9UFqbKZhPy6RqFEr4PnsQDBvrm/5MNG8p0jDgTd5DpN56OGaUwEYMM+6pBMq73/oUAZHAnZdlZPMI4lNKRWNgGK9H5bZORwudgxoh+2aqn2CRzb+5/ukUXR731mA0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=cr8Tapk5; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cr8Tapk5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1782128889; x=1813664889; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JJl24Emz4h3SZMr+NKGGApmvGaEAa8iddIdzOoS2KrE=; b=cr8Tapk5JuQkxCtGqbOVXaUNQLQH/dZRi0XD+IMppQvg7r/inwvpqnaw 32H2otdeiZOw1Nsjfyry0Hn93ZZbDWFy+diSSHXGtOVLw40Kd6rAQGej2 Bv1vbJEugl6R/XGePJ7u+Swq+to71GG5t/8HBfek0sWc2/hkf+HZ3xbMn CbbL0Ic1PNop/Tlw153VzvAafXDXxhHjmVtdyWU4EJeEWWUDP8Lq/Idsx xje3DMCzbDtH9l5Y+C3TQ0S+iWE82hPHkvMyy23kZhxhf8fS1TNj9Vfev RwzkJX1kyQqCZQTVGIFH4Al5y0SExpw5rj8kWbevY1Uw/h5go32iYLyGS w==; X-CSE-ConnectionGUID: bdWh8kWJRMmIEP6qG1Xu1A== X-CSE-MsgGUID: XdkrZLcSQii/pn29Tdfhzg== X-IronPort-AV: E=McAfee;i="6800,10657,11824"; a="93510052" X-IronPort-AV: E=Sophos;i="6.24,218,1774335600"; d="scan'208";a="93510052" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jun 2026 04:48:09 -0700 X-CSE-ConnectionGUID: FNn8ugijSA+46XyrOl3KDA== X-CSE-MsgGUID: iKNpXPDKRxSeMudjjY2UeQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,218,1774335600"; d="scan'208";a="272909378" Received: from black.igk.intel.com ([10.91.253.5]) by fmviesa002.fm.intel.com with ESMTP; 22 Jun 2026 04:48:06 -0700 From: Heikki Krogerus To: Rodrigo Vivi Cc: Matthew Brost , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Raag Jadav , "Michael J . Ruhl" , Andy Shevchenko , Mika Westerberg , Riana Tauro , David Airlie , Simona Vetter , dri-devel@lists.freedesktop.org, intel-xe@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/2] drm/xe/mcu_i2c: Take over control of the controller enabling Date: Mon, 22 Jun 2026 13:47:59 +0200 Message-ID: <20260622114759.3464047-3-heikki.krogerus@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260622114759.3464047-1-heikki.krogerus@linux.intel.com> References: <20260622114759.3464047-1-heikki.krogerus@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Some platforms make an assumption that the i2c controller's enabled state indicates also the power state of the controller. This can create a problem when the controller is in disabled state, because the hardware may assume incorrectly that it is then also in low-power state. To fix this, the controller is kept enabled by taking over the IC_ENABLE register. The controller has to be disabled when the configuration is updated and when the target address or the slave address are assigned, so disabling it when IC_CON, IC_TAR or IC_SAR registers are programmed, and then re-enabling it again. Signed-off-by: Heikki Krogerus --- drivers/gpu/drm/xe/xe_i2c.c | 65 +++++++++++++++++++++++++++++++++++-- drivers/gpu/drm/xe/xe_i2c.h | 1 + 2 files changed, 64 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_i2c.c b/drivers/gpu/drm/xe/xe_i2c.c index 732ad6ee05e9c..45fa9094b6142 100644 --- a/drivers/gpu/drm/xe/xe_i2c.c +++ b/drivers/gpu/drm/xe/xe_i2c.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -261,11 +262,49 @@ static void xe_i2c_remove_irq(struct xe_i2c *i2c) irq_domain_remove(i2c->irqdomain); } +#define IC_CON 0x00 +#define IC_TAR 0x04 +#define IC_SAR 0x08 +#define IC_ENABLE 0x6c +#define IC_ENABLE_STATUS 0x9c + +/* See "Disabling DW_apb_i2c" in the DesignWare DW_abp_i2c databook. */ +static int xe_i2c_disable(struct xe_i2c *i2c) +{ + int timeout = 100; + u32 status; + + do { + /* Disable.*/ + xe_mmio_rmw32(i2c->mmio, XE_REG(IC_ENABLE + I2C_MEM_SPACE_OFFSET), 1, 0); + + /* Verify. */ + status = xe_mmio_read32(i2c->mmio, XE_REG(IC_ENABLE_STATUS + I2C_MEM_SPACE_OFFSET)); + if (!(status & 1)) + return 0; + + /* Repeat. */ + usleep_range(25, 250); + } while (timeout--); + + return -ETIMEDOUT; +} + static int xe_i2c_read(void *context, unsigned int reg, unsigned int *val) { struct xe_i2c *i2c = context; - *val = xe_mmio_read32(i2c->mmio, XE_REG(reg + I2C_MEM_SPACE_OFFSET)); + switch (reg) { + case IC_ENABLE: + *val = i2c->ic_enable; + break; + case IC_ENABLE_STATUS: + *val = i2c->ic_enable & 1; /* NOTE: Checking only the enable bit */ + break; + default: + *val = xe_mmio_read32(i2c->mmio, XE_REG(reg + I2C_MEM_SPACE_OFFSET)); + break; + } return 0; } @@ -273,8 +312,30 @@ static int xe_i2c_read(void *context, unsigned int reg, unsigned int *val) static int xe_i2c_write(void *context, unsigned int reg, unsigned int val) { struct xe_i2c *i2c = context; + int ret; - xe_mmio_write32(i2c->mmio, XE_REG(reg + I2C_MEM_SPACE_OFFSET), val); + switch (reg) { + case IC_CON: + case IC_TAR: + case IC_SAR: + /* Disable the controller. */ + ret = xe_i2c_disable(i2c); + if (ret) + return ret; + + /* Write the register. */ + xe_mmio_write32(i2c->mmio, XE_REG(reg + I2C_MEM_SPACE_OFFSET), val); + + /* Enable the controller. */ + xe_mmio_rmw32(i2c->mmio, XE_REG(IC_ENABLE + I2C_MEM_SPACE_OFFSET), 0, 1); + break; + case IC_ENABLE: + i2c->ic_enable = val; + break; + default: + xe_mmio_write32(i2c->mmio, XE_REG(reg + I2C_MEM_SPACE_OFFSET), val); + break; + } return 0; } diff --git a/drivers/gpu/drm/xe/xe_i2c.h b/drivers/gpu/drm/xe/xe_i2c.h index fdbad51950423..e28279f0ebec7 100644 --- a/drivers/gpu/drm/xe/xe_i2c.h +++ b/drivers/gpu/drm/xe/xe_i2c.h @@ -36,6 +36,7 @@ struct xe_i2c { struct platform_device *pdev; struct i2c_adapter *adapter; struct i2c_client *client[XE_I2C_MAX_CLIENTS]; + unsigned int ic_enable; struct notifier_block bus_notifier; struct work_struct work; -- 2.50.1